参数资料
型号: R5F71474AK64FPV
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 27/123页
文件大小: 6757K
代理商: R5F71474AK64FPV
192
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
23. ADC - Analog to Digital Converter
23.1
Features
10-bit Resolution
0.5 LSB Integral Non-linearity
±2 LSB Absolute Accuracy
13s - 260s Conversion Time (50kHz to 1MHz ADC clock)
Up to 15ksps at Maximum Resolution (200kHz ADC clock)
Eight Multiplexed Single Ended Input Channels
Optional Left Adjustment for ADC Result Readout
0 - V
CC ADC Input Voltage Range
Selectable 1.1V ADC Reference Voltage
Free Running or Single Conversion Mode
ADC Start Conversion by Auto Triggering on Interrupt Sources
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
23.2
Overview
The Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P features a 10-bit succes-
sive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows eight single-
ended voltage inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant
level during conversion. A block diagram of the ADC is shown in Figure 23-1.
The ADC has a separate analog supply voltage pin, AVCC. AV
CC must not differ more than ±0.3V from VCC. See
the paragraph ”ADC Noise Canceler” on page 198 on how to connect this pin.
Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage reference may be exter-
nally decoupled at the AREF pin by a capacitor for better noise performance.
The Power Reduction ADC bit, PRADC, in ”PRR – Power Reduction Register” on page 42 must be written to zero
to enable the ADC module.
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