参数资料
型号: R5F71474AK64FPV
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 22/123页
文件大小: 6757K
代理商: R5F71474AK64FPV
187
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the counter to increment by one,
provided that the USICS1...0 bits are set to zero and by doing so the software clock strobe option is selected. The
output will change immediately when the clock strobe is executed, i.e., in the same instruction cycle. The value
shifted into the Shift Register is sampled the previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a
Clock Select Register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-
bit counter (see Table 21-2 on page 186).
Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0. The toggling is inde-
pendent of the setting in the Data Direction Register, but if the PORT value is to be shown on the pin the DDRE4
must be set as output (to one). This feature allows easy clock generation when implementing master devices. The
bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC
strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when oper-
ating as a master device.
1
0
External, negative edge
External, both edges
1
0
1
External, positive edge
Software clock strobe (USITC)
1
External, negative edge
Software clock strobe (USITC)
Table 21-2.
Relations between the USICS1:0 and USICLK setting. (Continued)
USICS1
USICS0
USICLK
Shift Register Clock Source
4-bit Counter Clock Source
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