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参数资料
| 型号： | R5F71474BD80FPV |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 14/123页 |
| 文件大小： | 6757K |
| 代理商： | R5F71474BD80FPV |
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179
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
The Three-wire mode timing is shown in Figure 21-3 on page 178 At the top of the figure is a USCK cycle refer-
ence. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for
both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is
changed (Data Register is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the oppo-
site edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. The USI clock
modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 21-3 on page 178), a bus transfer involves the following steps:
1.
The Slave device and Master device sets up its data output and, depending on the protocol used, enables
its output driver (mark A and B). The output is set up by writing the data to be transmitted to the Serial Data
Register. Enabling of the output is done by setting the corresponding bit in the port Data Direction Register.
Note that point A and B does not have any specific order, but both must be at least one half USCK cycle
before point C where the data is sampled. This must be done to ensure that the data setup requirement is
satisfied. The 4-bit counter is reset to zero.
2.
The Master generates a clock pulse by software toggling the USCK line twice (C and D). The bit value on
the slave and master’s data input (DI) pin is sampled by the USI on the first edge (C), and the data output is
changed on the opposite edge (D). The 4-bit counter will count both edges.
3.
Step 2. is repeated eight times for a complete register (byte) transfer.
4.
After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer is com-
pleted. The data bytes transferred must now be processed before a new transfer can be initiated. The
overflow interrupt will wake up the processor if it is set to Idle mode. Depending of the protocol used the
slave device can now set its output to high impedance.
21.3.2
SPI Master Operation Example
The following code demonstrates how to use the USI module as a SPI Master:
SPITransfer:
sts
USIDR,r16
ldi
r16,(1<<USIOIF)
sts
USISR,r16
ldi
r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
SPITransfer_loop:
sts
USICR,r16
lds
r16, USISR
sbrs
r16, USIOIF
rjmp
SPITransfer_loop
lds
r16,USIDR
ret
The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK
pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is
transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back
into the r16 Register.
The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and
fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK.
The loop is repeated 16 times.
The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4):
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