参数资料
型号: R8J73540BGZV
厂商: Renesas Electronics America
文件页数: 2/46页
文件大小: 0K
描述: SH-MOBILE, PB-FREE
产品培训模块: Electromagnetic Noise Reduction Techniques Part 1
标准包装: 1
系列: SH-Mobile
核心处理器: SH-4A
芯体尺寸: 32-位
速度: 216MHz
连通性: I²C
外围设备: DMA,LCD,WDT
输入/输出数: 144
程序存储器类型: ROMless
RAM 容量: 16M x 8
电压 - 电源 (Vcc/Vdd): 1.15 V ~ 1.3 V
封装/外壳: 模块
包装: 托盘
8
SuperH
Family of Microcontrollers & Microprocessors
I Total upward code compatibility
The roadmap for the SuperH processor product
line is upwardly code compatible. This
compatibility enables a faster time-to-market
with further amortization of prior engineering
investment and preservation of previously
written software.
Processor choice from 10 to 1080 MIPS
Large selection of devices within each family
I Best code efficiency
16-bit instruction length for high code
density
Up to 40% less memory footprint than
32-bit instructions
Up to 40% more data in cache than
32-bit instructions
Twice the number of instructions loaded
on the SDRAM bus
SH-1
SH-2
SH-3
SH-4
SuperH
Non-DSP
Instructions
DSP
Instruc-
tions
MIPS
NEC
IDT
Toshiba
PowerPC
IBM
Fr
ee
S
cale
ARM
ARM7
Atmel/Cirru
s
ARM9
Fr
ee
S
cale
XScale
Intel
Upward Code Compatibility
1.5
RELATIVE
VALUE
1.0
SuperH
(16-bit fixed)
1.24
V830
(32-bit variable)
1.28
MIPS64
(32-bit fixed)
1.44
ARM
(32-bit fixed)
1.5
PowerPC
(32-bit fixed)
0.5
1.0
C Object Size Comparison
SuperH Code Efficiency
Higher Execution
Performance
Superscalar gives
1.5x more performance
at the same MHz
SH-2A = 6x the
performance of SH-2
Faster Interrupt
Response Time
SH-2: 37 cycles;
SH-2A: 6 cycles
SH-2A = 1/25 the
response time of SH-2
Denser Program Code Size
Improved C compiler
and additions to
instruction set provide
25% code size reduction
Relative Value
6
5
4
3
2
1
0
SH-2
@50MHz
SH-2A
@160MHz
SH-2A
@200MHz
4.8x
6x
Relative Value
1
0.75
0.50
0.25
0
SH-2 @ 50MHz
SH-2A @ 200MHz
1/25x
SH-2A
Relative Value
1
0.75
0.50
0.25
0
SH-2
0.75x
SH-2A Enhancements
TOP REASONS TO SELECT SuperH
91 Instructions
103 Instructions
Instruction Set
Architecture
Shared Bus
SuperHyway
3 Independent
Buses
Greater Bandwidth
Bus Architecture
16/32 KB I/O Cache
2-Way
Set-Associative
32/32 KB I/O Cache
4-Way
Set-Associative
Larger Cache Size
5-Stage Pipeline
10-Stage Pipeline
Improved FPU
Architecture
Superscalar
5-Stage Pipeline
Superscalar
7-Stage Pipeline
Improved Micro-
Architecture
240 MHz @ 1.5V
600 MHz @ 1.25V
Higher Performance
at Lower Power
SH-4
SH-4A
SH-4A Enhancements
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