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参数资料
| 型号： | R8J73540BGZV |
| 厂商： | Renesas Electronics America |
| 文件页数： | 4/46页 |
| 文件大小： | 0K |
| 描述： | SH-MOBILE, PB-FREE |
| 产品培训模块： | Electromagnetic Noise Reduction Techniques Part 1 |
| 标准包装： | 1 |
| 系列： | SH-Mobile |
| 核心处理器： | SH-4A |
| 芯体尺寸： | 32-位 |
| 速度： | 216MHz |
| 连通性： | I²C |
| 外围设备： | DMA，LCD，WDT |
| 输入/输出数： | 144 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 16M x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.15 V ~ 1.3 V |
| 封装/外壳： | 模块 |
| 包装： | 托盘 |
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10
SuperH
Family of Microcontrollers & Microprocessors
I SuperH has 2D and 3D
graphics capabilities
SuperH RISC and RISC/FPU
microprocessors have excellent
graphics-handling capabilities,
allowing consumer-level prod-
ucts
with
highly
integrated,
enhanced features at popular
prices. Systems built with other
processor architectures require a
separate graphics chip, which
would increase complexity and
add cost.
Superscalar architecture
(SH-2A, SH-4, and SH-4A) –
Allows FPU operations to occur
independently from non-FPU
operations of the system. This
optimizes the performance of the
graphics calculations and minimizes
flicker and graphic stalling.
Pair single-precision data transfer –
Data transfer can be performed by
pair single-precision data transfer
instructions, which enable two
single-precision (each 32-bit) data
items to be transferred for double
the transfer performance.
Vector/matrix calculation – Data can be processed
efficiently because four multiplication operations and
one addition operation are performed in parallel.
Geometric-operation instructions – To enable high-speed
computation with a minimum of hardware, geometric-
operation instructions perform approximate-value computa-
tions.
The SH-4 supports two 32-byte store queues (SQ) to perform
high-speed burst writes to external memory. While the
contents of one SQ are being transferred to external memory,
the other SQ can be written to without a penalty cycle. This
functionality is especially useful to transfer video, graphic or
display list data to the frame buffer of the graphic processor.
I SuperH MCU flash technology leadership
Fourth-generation embedded flash, introduced in 2002,
features single-cycle access to on-chip flash memory.
0.18m process, flash size as high as 1MB
Access as fast as 12.5ns @ 80MHz
Up to -40°C to +125°C range
Minimum endurance up to 10,000 erase/write cycles
Graphic Processor
CPU
Interface
Frame
Buf
fer
Interface
DIRECT ACCESS
Geometry
Processor
Display
Controller
PRIMITIVES
OF DISPLAY
LIST
Frame
Buf
fer
SDRAM
SQ 1-32 Bytes
SH-4
SQ 2-32 Bytes
Local
S
H
Bu
s
Display
80MHz
100MHz
Next-Gen
NVMs
50MHz
(180nm)
(150nm)
80MHz
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
Stack (NOR)
80MHz
(150nm)
Memory
Structure
NOR
100MHz
(130nm)
(90nm)
133MHz
(65nm)
166MHz
(45nm)
New
NVM
New
NVM
MRAM
MONOS
Metal Oxide
Nitride Oxide
Silicon
100MHz
(0.2- 0.18m)
M
Fast Data Transfers to Frame Buffers
Using the SH-4 Store Queues
SuperH Flash Roadmap
TOP REASONS TO SELECT SuperH
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