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参数资料
| 型号： | RD-19230FG-203 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP64 |
| 封装： | 0.520 X 0.520 INCH, GREEN, PLASTIC, QFP-64 |
| 文件页数： | 17/23页 |
| 文件大小： | 476K |
| 代理商： | RD-19230FG-203 |
3
Data Device Corporation
www.ddc-web.com
RD-19230
W-05/08-0
Logic 0 = 0.8 V max. / Logic 1 = 2.0 V min.
Loading=10 A max P.U. current source to +5 V || 5 pF max., CMOS transient protected
Logic 0 inhibits; Data stable within 150 ns (Logic 1 = Transparent)
{ Logic 0 enables; Data stable within 150 ns (Logic 0 = Transparent)
{ Logic 1 = High Impedance; Data High Z within 100 ns (Note 8)
Mode
D1
D0
Resolution
Resolver
0
10 bits
“
0
1
12 bits
“
1
0
14 bits
“
1
16 bits (Preset, Note 10)
LVDT
-5 V
0
8 bits
“
0
-5 V
10 bits
“
1
-5 V
12 bits
“
-5 V
14 bits
Logic 0 enables ZIP, Logic 1 enables CB
Logic 0 = 1.5 V max., Logic 1 = 3.5 V min., negative voltage = -3.5 V min.
Logic 1 selects VEL1 components, Logic 0 selects VEL2 components
Logic 0, precharged components gain is 4
Logic 1, precharged components gain is 1/4
Logic 0 enables encoder emulation, Falling edge latches encoder resolution
(note 5)
45 max. from 400 Hz to 10kHz
deg
DIGITAL INPUTS (Note 10)
TTL / CMOS COMPATIBLE INPUTS
Inhibit (INH)
Enable Bits 1 to 8 (EM) }
Enable Bits 9 to 16 (EL) }
Resolution and Mode Control (D1 & D0)
(See Notes 1 & 2)
ZIP_EN
CMOS Compatible Inputs
SHIFT
UP/DN
A QUAD B
SYNTHESIZED REFERENCE
±Sig/Ref Phase Shift Correction
(+S, -S, SIN, +C, -C, COS)
Resolver, differential, groundbased
2 ±15%
±25 continuous (Note 13)
10M min. || 10 pF.
Vrms
Vp
Ω
SIGNAL INPUT
Type
Voltage: operating
overload
Input impedance
(+RH, -RL)
Differential
10 max. (Note 11)
±5 max. (1.5 min.)(Note 11)
±25 continuous; ±100 transient (Note 13)
DC to 10k (Note 4)
10M min. || 20 pf
3
Vp-p
Vp
Hz
Ω
Vp
REFERENCE
Type
Voltage: differential
single ended
overload
Frequency
Input Impedance
Common Mode Range
10, 12, 14, or 16 (Note 1 & 2)
Bits
RESOLUTION
VALUE
UNIT
PARAMETER
These specs apply over the rated power supply, temperature,and reference frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion.
TABLE 1. RD-19230 SPECIFICATIONS
4 +1 LSB
2 +1 LSB
± 1
4 +1 LSB
2 +1 LSB
± 1
5 +1 LSB
3 +1 LSB
± 2
47-1k (Note 4)
1k - 4k
4k - 10k
1 +1 LSB
± 1
1 +1 LSB
± 1
47-1k (Note 4)
1k - 5k
FREQUENCY RANGE
ACCURACY
-XX2 (Note 3)
-XX3 (Note 3)
Repeatability
Differential Linearity
FREQUENCY RANGE
ACCURACY
-XX5 (Note 3)
Repeatability
Differential Linearity
Hz
minutes
LSB
Hz
minutes
LSB
5k - 10k
3 +1 LSB
± 2
DIGITAL OUTPUTS
Drive Capability
Parallel Data (1-16) (see note 14)
Converter Busy (CB)
Zero Index Pulse (ZIP)
50 pF+
Logic 0: 1 TTL load, 1.6 mA at 0.4 V max.
Logic 1; 10 TTL loads, = 0.4 mA at 2.8 V min.
Logic 0; 100 mV max. driving CMOS
Logic 1; +5 V supply minus 100 mV min. driving CMOS High Z; 10 A || 5 pF max. (Note 8)
10, 12, 14, or 16 parallel lines; natural binary angle positive logic (see note 2)
0.25 to 0.75 s positive pulse leading edge initiates counter update. (CB functions with
ZIP_EN pin tied to +5 V or NC), Logic 1 at all 0’s
This output is active when the ZIP_EN pin is tied to GND (Logic 0).
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