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参数资料
| 型号： | RD-19230FG-203 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP64 |
| 封装： | 0.520 X 0.520 INCH, GREEN, PLASTIC, QFP-64 |
| 文件页数： | 5/23页 |
| 文件大小： | 476K |
| 代理商： | RD-19230FG-203 |
13
Data Device Corporation
www.ddc-web.com
RD-19230
W-05/08-0
2
1
-VCO
VEL
+5 V
-5 V
100 k
Ω
(OFFSET)
100 RV
0.8 RV
0.4 R (SCALING)
V
RD-19230
FIGURE 15. VELOCITY TRIMMING
DC INPUTS
As noted in TABLE 1, the RD-19230 accepts DC inputs. DC input
operation is from 0° to 180° or 180° to 359° only, due to the pos-
sibility of an unstable false null, i.e., 180° hangup. The false null
condition will only happen on power up and an instantaneous
180° step, therefore once the converter moves it will go to the
correct answer. In real world applications where an instanta-
neous 180° change is impossible, the converter will always be
correct within 360°. The problem arises at power up in real sys-
tems. If the converter powers up at exactly 180° from the applied
input, the converter will not move. This is very unlikely, although
it is theoretically possible. This condition is most often encoun-
tered during wraparound verification tests, simulations, or trou-
bleshooting.
It is recommended that the synthesized reference option be dis-
abled for DC input operation. Disable the synthesized reference
by connecting pin 52, DSR, to ground through a 10 ohm resistor.
The reference input is set to DC by tying RH to +5V and RL to
ground or -5V.
Set the COS and SIN inputs such that the maximum signal is
equal to 1.8VDC. For example, at 90° the SIN input should equal
to 1.8VDC. This will keep the BW hysteresis consistent with AC
operation.
Input offsets will affect accuracy. Verify the COS and SIN inputs
do not have DC offsets. If offsets are present, a differential op
amp configuration can be used to minimize differential offset
problems.
Bit output is undetermined during DC operation and should not
be used.
Choose the bandwidth value of the converter based on the rate
of change of the systems input amplitude variation. It should be
large enough to minimize it’s effect on the system dynamics.
Note that if the bandwidth is too high the system will be more
susceptible to noise.
The accuracy of a converter using a DC input will be degraded
from the rated accuracy. Consider the best case where the
input is single ended and no additional DC offsets are present
on the input of the converter - the accuracy will degrade by
about 2 arc minutes. For example, if a part is rated at 2 arc min-
utes, a DC input will degrade the accuracy to approximately 4
arc minutes.
VELOCITY TRIMMING
The RD-19230 specifications for velocity scaling, reversal error,
and offset are listed in TABLE 1. Velocity scaling and offset are
externally trimmable for applications requiring tighter specifica-
tions than those available from the standard unit. FIGURE 15
shows the setup for trimming these parameters with external
pots. It should also be noted that when the resolution is changed,
velocity scaling is also changed.
OPTIONAL BANDWIDTH COMPONENTS
The RD-19230 provides the option of using a second set of
bandwidth components. The second set of components can be
used for switch-on-the-fly or dual-bandwidth applications. The
SHIFT and UP/DN inputs are used when switching bandwidth
components, and their operation is described below. Refer to the
block diagram, FIGURE 1.
SHIFT
The SHIFT pin is an input that chooses between the VEL1 and
VEL2 bandwidth components. This pin has an internal pull-up
to +5V. When the SHIFT pin is left open, or a logic 1 is applied,
the VEL1 components are selected. When a Logic 0 is applied,
the VEL2 components are selected. The deselected set of
bandwidth components are driven by an amplifier, with pro-
grammable gain, that follows the velocity amplifier. This ampli-
fier can be used to precharge the deselected set of compo-
nents to the voltage level that is expected after a change in res-
olution. (See description on BENEFIT OF SWITCHING RESO-
LUTION ON THE FLY.)
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