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参数资料
| 型号： | RD-19230FX-202T |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP64 |
| 封装： | 0.520 X 0.520 INCH, PLASTIC, QFP-64 |
| 文件页数： | 7/23页 |
| 文件大小： | 476K |
| 代理商： | RD-19230FX-202T |
15
Data Device Corporation
www.ddc-web.com
RD-19230
W-05/08-0
DATA
VALID
150 nsec max
INHIBIT
100 nsec MAX
ENABLE
150 nsec MAX
DATA
VALID
HIGH Z
For 16-bit bus, EM/EL may be tied to ground for transparent mode, as long
as only 1 R/D channel is used on the data bus.
250 to 750 nsec
CB
50 nsec
DATA
VALID
DATA
VALID
* Next CB pulse cannot occur
for a minimum of 150 nsec.
1 / ( 40 x Fs )
FIGURE 18. INHIBIT TIMING
FIGURE 19. ENABLE TIMING
FIGURE 20. CONVERTER BUSY TIMING
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 18,
angular output data is valid 150 ns maximum after the applica-
tion of the negative inhibit pulse.
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bits. As
shown in FIGURE 19, output data is valid 150 ns maximum after
the application of a negative enable pulse. The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSB. As shown in FIGURE 20,
output data is valid 50 nS maximum after the middle of the CB
pulse. CB pulse width is 1/( 40 x FS ),which is nominally 375 ns.
Note: The converter INH may be applied regardless of the
CB line state. If the CB is busy the converter INH will wait for
timing referenced to CB (Fig.20), before setting the INH
latch. Therefore when applying an inhibit signal to the con-
verter there is no need to monitor the CB line.
FIGURE 17. BENEFIT OF SWITCHING
RESOLUTION ON THE FLY
Without Switch Resolution on the Fly Implemented
With Switch Resolution on the Fly Implemented
FIGURE 16 for an example of the input wiring connections
necessary for switching on the fly between 14 and 16 bit res-
olution.
DUAL BANDWIDTHS
With the second set of BW component pins, the user can set two
bandwidths for the RD-19230 and choose between them. To use
two bandwidths, proceed as follows:
1) Tie UP/DN to pin -5V.
2) Choose the two bandwidths following the guidelines in the
General Setup Considerations; the RV resistor must be the
same value for both bandwidths.
3) Use the SHIFT pin to choose between bandwidths. A logic 1
selects the VEL1 components and a logic 0 selects the VEL2
components.
VEL
0V
-5V
ERROR 0
D0
0V
5V
BIT
0V
5V
ERROR = 13.6 LSBs per box
Depending on the bandwidth, the step error may be greater. Also, less
velocity / movement will lessen the error glitch. The graphs above shows
a worst case condition based on one bandwidth and tracking rate setup.
Worst case is when the velocity overshoot hits the saturations point.
VEL
0V
-5V
ERROR 0
D0
0V
5V
BIT
0V
5V
ERROR = 1500 LSBs per box
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相关代理商/技术参数 |
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| RD-19230FX-203 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Resolver-to-Digital Converter |
| RD-19230FX-203T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:RESOLVER-TO-DIGITAL CONVERTER |
| RD-19230FX-302 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Resolver-to-Digital Converter |
| RD-19230FX-302T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Resolver-to-Digital Converter |
| RD-19230FX-303 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Resolver-to-Digital Converter |
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