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参数资料
| 型号： | RD-19230FX-202T |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP64 |
| 封装： | 0.520 X 0.520 INCH, PLASTIC, QFP-64 |
| 文件页数： | 8/23页 |
| 文件大小： | 476K |
| 代理商： | RD-19230FX-202T |
16
Data Device Corporation
www.ddc-web.com
RD-19230
W-05/08-0
INTERNAL ENCODER EMULATION
The RD-19230 can be programmed to encoder emulation mode
by toggling the A_QUAD_B input to a logic 0. The U/B output pin
becomes B (LSB XOR LSB + 1). The A (LSB + 1) and B output
signals can be used in control systems that are designed to inter-
face with incremental optical encoders. To enable the Zero Index
pulse, ZIP_EN should be tied to a logic 0.
An example circuit to create a low going edge of A_QUAD_B is
depicted in Figure 23B. If the power supply takes longer than
50ms to start up then the time constant of 50ms set in FIGURE
23B must be extended. Alternatively a system logic reset signal
or internally generated logic ‘load’ pulse can be generated to
latch in the encoder resolution.
The resolution of the incremental outputs is latched from the D0
and D1 inputs on the low going edge of A_QUAD_B. The resolu-
tion of the parallel data outputs may be changed any time after
the encoder resolution is latched (see FIGURE 23).
When in A_QUAD_B mode, the resolution of the parallel data
can be changed to a resolution equal to or greater than the
A_QUAD_B resolution setting only. For example if the
A_QUAD_B mode is active and the resolution is set to 12 bits,
the resolution of the parallel programmed data can be changed
from 12 bits to 14- or 16-bits by setting D0 & D1. If 10-bit mode
is required for the parallel data, the A_QUAD_B resolution must
also be programmed to 10-bits.
Note: The encoder resolution must be less than or equal to
the resolution of the parallel data outputs. Refer to
FIGURE 21.
The timing of the A, B and ZIP (or North Reference Pole [NRP])
output
is
dependent
on
the
rate
of
change
of
the
synchro/resolver position (rps or degrees per second) and the
encoder resolution latched into the RD-19230 (refer to
FIGURE 22). The calculations for the timing are:
n = resolution of parallel data
t = 1 / ( 2n* Velocity(RPS))
T = 1 / ( Velocity(RPS))
Note: The Z1 pulse is high when all the bits of the counter
are zero. If the resolution of the counter, (parallel data)
is programmed differently than that of the A_QUAD_B
then the resolution of the counter will determine the
resolution of the ZIP.
CLARIFICATION OF A_QUAD_B, U/B AND
ZIP_EN FUNCTIONS
The RD-19230 is a tracking converter which is designed with a
Type II closed servo loop. The Type II closed servo loop has an
internal incremental integrator. This integrator acts as an up-
down position counter. An AC error (e) within the RD-19230 rep-
resents the difference between
θ (current angle to be digitized)
and
φ (the angle stored in digital form in the up-down counter).
Because the RD-19230 constitutes in itself a Type II closed loop
servomechanism, it continuously attempts to null the error to
zero. This is accomplished by counting up or down 1 LSB until
φ
is equal to
θ thus having an error of zero.
When A_QUAD_B is logic 0, encoder emulation mode is select-
ed (i.e. The U/B output [Pin 29] is programmed to B). The
encoder emulator resolution is set on the falling edge of
A_QUAD_B (see TABLE 7).
When A_QUAD_B is logic 1, encoder emulation mode is not
selected (i.e. The U/B output is set to U, which indicates the
direction of the internal position counter).
Note: U indicates the “UP” direction of the counter. If the RD-
19230 is at a static angle awaiting a new angle
θθ,, U indi-
cates the direction the counter was going to get to the
current angle
φφ. As the error is approaching zero, the
internal analog circuitry voltage may overshoot before
settling - which would then indicate an incorrect direc-
tion. Because of this overshoot, the U output should
not be relied on after settling to a static state. Only dur-
ing active resolver movement will the U output state be
reliable. U is a logic 1 when going in the positive direc-
tion (increasing angle). It is a logic 0 when going in the
negative direction (decreasing angle).
ZIP_EN chooses between the CB and Zero Index pulse outputs
and is independent of encoder emulation mode. A logic 1
enables the CB pulse, a logic 0 enables the Zero Index pulse
(see TABLE 8).
Note: When the RD-19230FX is set for 16-bit mode, the LSB
is bit 16. When the RD-19230FX is set for 14-bit mode,
the LSB is bit 14 and bits 15 and 16 are set to logic “0”.
(See TABLE 1, NOTE 1).
TABLE 7. A_QUAD_B (PIN 30) FUNCTION
A_QUAD_B (PIN 30)
U/B (PIN 29)
0
B
1
U
TABLE 8. ZIP_EN (PIN 55) FUNCTION
ZIP_EN (PIN 55)
CB/ZI (PIN 31)
0
ZI
1
CB
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