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| 型号： | RD-19240FSA00T |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP52 |
| 封装： | PLASTIC, MQFP-52 |
| 文件页数： | 13/18页 |
| 文件大小： | 215K |
| 代理商： | RD-19240FSA00T |
4
Data Device Corporation
www.ddc-web.com
RD-19240
Pre 1-1-04/05-0
APPLICATIONS
The low cost, small size, high accuracy, and versatile perfor-
mance of the RD-19240 converter make it ideal for use in mod-
ern high performance industrial and automotive control systems.
It is ideal for users who wish to use a resolver input in their
encoder-based system. Typical applications include motor con-
trol, factory automation, hybrid electric vehicles, and steering.
THEORY OF OPERATION
The RD-19240 converter is a single CMOS custom monolithic
chip. It is implemented using mixed signal CMOS technology
which merges precision analog circuitry with digital logic to form
a complete high-performance tracking resolver-to-digital convert-
er. For user flexibility and convenience, the converter bandwidth,
dynamics, and velocity scaling are externally set with passive
components.
FIGURE 1 is the RD-19240 Functional Block Diagram. The con-
verter operates with ±5 V DC power supplies. Analog signals are
referenced to analog ground, which is at ground potential. The
converter is made up of two main sections; a converter and a dig-
ital interface. The converter front-end consists of sine and cosine
differential input amplifiers. These inputs are protected to ±25 V
with 2 k
resistors and diode clamps to the ±5 V DC supplies.
These amplifiers feed the high accuracy Control Transformer
(CT). Its other input is the 14-bit digital angle
φ. Its output is an
analog error angle, or difference angle, between the two inputs.
The CT performs the ratiometric trigonometric computation of
SIN
θCOSφ - COSθSINφ = SIN(θ-φ) using amplifiers, switches,
logic and capacitors in precision ratios.
Note: The error output of the CT is normally sinusoidal, but
in LVDT mode, it is triangular (linear) and can be used
to convert any linear transducer output.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. For enhanced accuracy, the CT in
these converters uses capacitors in precision ratios, instead of
the more conventional precision resistor ratios. Capacitors used
as computing elements with op-amps need to be sampled to
eliminate voltage drifting. Therefore, the circuits are sampled at a
high rate (70 kHz) to eliminate this drifting and at the same time
to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The DC error is
integrated yielding a velocity voltage which in turn drives a volt-
age-controlled oscillator (VCO). This VCO is an incremental inte-
grator (constant voltage input to position rate output) which,
together with the velocity integrator, forms a type II servo feed-
back loop. A lead in the frequency response is introduced to sta-
bilize the loop, and a lag at higher frequency is introduced to
PARAMETER
VALUE
UNIT
TABLE 1. RD-19240 SPECIFICATIONS (CONT.)
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
V
%
V
mA
(notes 6, 7 and 9)
+5
-5
±5
+7
-7
14 typ, 22 max (each)
TEMPERATURE RANGE
Operating (case)
-AXX
-2XX
Storage
°C
-40 to +125
-40 to +85
-65 to +150
PHYSICAL
CHARACTERISTICS
Size
FS Package
52-pin MQFP
LS Package
64-pad plastic LPCC
in(mm)
0.39 x 0.39 (10.0 x 10.0)
0.35 x 0.35 (9.0 x 9.0)
MOISTURE SENSITIVITY
LEVEL (STANDARD PORT)
Level 2 tested in accordance with
JDEC spec J-STD-020
DYNAMIC
CHARACTERISTICS
Resolution
Tracking Rate-min (note 4)
Bandwidth(Closed Loop) Max
Ka (acceleration constant
- see note 2)
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time(179° step)
bits
rps
Hz
1/sec2
1/sec
deg/s2
msec
(at maximum bandwidth)
10
12
14
1152
288
72
1200
600
5.7M
1.4M
19.5
4.9
295k
2400
1200
600
2M
500k
30k
28
20
DIGITAL INPUT/OUTPUT
(CONT) (NOTE 6)
A, B
Zero Index Pulse (ZIP)
Incremental Encoder Output
With the ZIP_EN pad tied to ground
“Logic 0,” this ZIP output is active
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range(Full Scale)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
Noise
V
%
PPM/C
%
mV
V/C
k
Vp/V
Positive for increasing angle
±4 (at nominal ps)
10 typ.
20 max.
100 typ.
0.75 typ. 1.3 max.
0.5 typ
5 typ.
10 max.
15 typ.
8 min.
1 typ.
TABLE 1 notes:
1. Unused data bits are set to logic “0”.
2. For Ka definition, see the RDC-19220/RD-19230 Series Converters Applications
Manual (MN-19220XX-001) acceleration lag section.
3. If the frequency is between 47Hz and 1kHz, then there may be 1 LSB of jitter at
quadrant boundaries.
4. See text, General Setup Considerations.
5. When using internally generated -5V the internal -5V charge pump when mea-
sured at the converter pad, may be as low as -20% (or -4V).
6. Any unused input pads may be left floating. All TTL and CMOS input pads are
internally pulled up to +5 volts.
7. High Z refers to parallel data only.
8. In LVDT mode, bit 12 is LSB for 10-bit mode resolution.
9. +5V supply is connected to pin 33 and the underside pad of the LPCC package.
See Mechanical drawing and pin-out table.
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