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7
Data Device Corporation
www.ddc-web.com
RD-19240
Pre 1-1-04/05-0
TYPICAL INPUT CONFIGURATION
FIGURE 6 illustrates a typical input configuration for a 2 Volt
Resolver input. However, other configurations may be used. Consult
the RD/RDC Series Converters Applications Manual (document
#MN-19220XX-001) for additional input configuration options.
DC INPUTS
As noted in TABLE 1 the RD-19240 accepts DC inputs. DC oper-
ation is from either 0° to 180° or 180° to 359°, due to the possibil-
ity of an unstable false null, i.e., 180° hangup condition. This unsta-
ble condition is corrected once the input angle is changed. In real
world applications, an instantaneous 180° change is impossible,
therefore the converter will always be correct within 360°.
If, however, a system is powered up at exactly 180° from the
applied input, the output angle may not respond. Although theo-
retically possible, this condition is highly unlikely in real world appli-
cations and is most often encountered during wraparound verifi-
cation tests, simulations and troubleshooting.
When using DC inputs, take into account the following considerations:
1. Disable the synthesized reference option by connecting pin
DSR to ground through a 10 ohm resistor.
2. Set the reference signal to DC by tying RH to +5 V and RL to
ground or -5 V.
3. Set the SIN and COS inputs such that the maximum signal
equals 1.8 VDC. To verify that the maximum signal is at the
proper voltage, monitor the SIN input at 90° and adjust the
reference voltage so that SIN equals 1.8 VDC. This will ensure
that the bandwidth hysteresis is consistent with AC operation.
4. The BIT signal will be an active low because the reference has
no AC component.
5. Converter accuracy will be degraded from the rated accuracy
when using a DC input. In the best case scenario, where the
input is single ended and there are no additional offsets pre-
sent.
VELOCITY TRIMMING
RD-19240 specifications for velocity scaling, reversal error, and
offset are contained in TABLE 1. Velocity scaling and offset are
externally trimmable for applications requiring tighter specifications
than those available from the standard unit. FIGURE 7 shows the
setup for trimming these parameters with external potentiometers.
It should also be noted that when the resolution is changed, veloc-
ity scaling is also changed. Since the VEL output is from an inte-
grator with capacitor feedback, the VEL voltage cannot change
instantaneously. Therefore, when changing resolution while mov-
ing, there will be a transient with a magnitude proportional to the
velocity and a duration determined by the converter bandwidth.
SYNTHESIZED REFERENCE
The synthesized reference section of the RD-19240 eliminates
errors due to phase shift between the reference and signal inputs.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage (e)
in the converter. Due to the inductive nature of synchros and
resolvers, their output signals lead the reference input signal (RH
and RL). When an uncompensated reference signal is used to
demodulate the control transformer’s output, quadrature voltages
are not completely eliminated. As shown in the block diagram,
FIGURE 1, the converter synthesizes its own internal reference
signal based on the SIN and COS signal inputs. Therefore, the
phase of the synthesized (internal) reference is determined by the
signal input, resulting in reduced quadrature errors.
TABLE 3. MAX TRACKING RATE (MIN) IN RPS
RC / RSET
(
)
RS / RCLK
(
)
RESOLUTION
10
12
14
30k** or open
30k
1152
288
72
23k
20k
1728
432
108
23k
15k
2304
576
*
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
*
10
15k
20k
23k
10
30k
23k
7
10
30k
30k** or open
14
12
10
RESOLUTION
RS / RCLK
(
)
RC / RSET
(
)
TABLE 4. CARRIER FREQUENCY (MAX) IN KHZ
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.