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参数资料
| 型号： | RD-19240LG200T |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC64 |
| 封装： | PLASTIC, LCC-64 |
| 文件页数： | 5/18页 |
| 文件大小： | 215K |
| 代理商： | RD-19240LG200T |
13
Data Device Corporation
www.ddc-web.com
RD-19240
Pre 1-1-04/05-0
When in A_QUAD_B mode, the resolution of the parallel data
can be changed to a resolution equal to or greater than the
A_QUAD_B resolution setting only. For example if the
A_QUAD_B mode is active and the resolution is set to 12 bits,
the resolution of the parallel programmed data can be changed
from 12 to 14 bits by using D0 & D1. If 10-bit mode is required for
the parallel data, the A_QUAD_B resolution must also be pro-
grammed to 10 bits.
Note: The encoder resolution must be less than or equal to
the resolution of the parallel data outputs. Refer to
FIGURE 15.
The timing of the A, B and ZIP (or North Reference Pole [NRP])
output
is
dependent
on
the
rate
of
change
of
the
synchro/resolver position (rps or degrees per second) and the
encoder resolution latched into the RD-19240 (refer to
FIGURE 16). The calculations for the timing are:
n = resolution of parallel data
t = 1 / ( 2n* Velocity(RPS))
T = 1 / ( Velocity(RPS))
Note: The Z1 pulse is high when all the bits of the counter
are zero. If the resolution of the counter, (parallel data)
is programmed differently than that of the A_QUAD_B
then the resolution of the counter will determine the
resolution of the ZIP.
CLARIFICATION OF A_QUAD_B, U/B AND
ZIP_EN FUNCTIONS
The RD-19240 is a tracking converter designed with a Type II
closed servo loop. The Type II closed servo loop has an internal
incremental integrator. This integrator acts as an up-down posi-
tion counter. An AC error (e) within the RD-19240 represents the
difference between
θ (current angle to be digitized) and φ (the
angle stored in digital form in the up-down counter). Because the
RD-19240 constitutes in itself a Type II closed loop servomech-
anism, it continuously attempts to null the error to zero. This is
accomplished by counting up or down 1 LSB until
φ is equal to θ
thus having an error of zero.
When A_QUAD_B is logic 0, encoder emulation mode is select-
ed (i.e. The U/B output [Pad 29] is programmed to B). The
encoder emulator resolution is set on the falling edge of
A_QUAD_B (see TABLE 8).
When A_QUAD_B is logic 1, encoder emulation mode is not
selected (i.e. The U/B output is set to U, which indicates the
direction of the internal position counter).
Note: U indicates the direction of the counter. It stands for
“UP”. If the RD-19240 is at a static angle awaiting a
new angle
θθ,, U indicates the direction the counter was
going to get to the current angle
φφ. As the error is
approaching zero, the internal analog circuitry voltage
may overshoot before settling - which would then indi-
cate an incorrect direction. Because of this overshoot,
the U output should not be relied on after settling to a
static state. Only during active resolver movement will
the U output state be reliable. U is a logic 1 when
going in the positive direction (increasing angle). It is
a logic 0 when going in the negative direction
(decreasing angle).
ZIP_EN chooses between the CB and Zero Index pulse outputs
and is independent of encoder emulation mode. A logic 1
enables the CB pulse, a logic 0 enables the Zero Index pulse
(see TABLE 8).
Note: When the RD-19240 is set for 14-bit mode, the LSB is
bit 14. When the RD-19240 is set for 12-bit mode, the
LSB is bit 12 and bits 13 and 14 are set to logic “0”.
(See TABLE 1, NOTE 1).
TABLE 7. A_QUAD_B (PAD 30) FUNCTION
A_QUAD_B (PAD 30)
U/B (PAD 29)
0
B
1
U
TABLE 8. ZIP_EN (PAD 55) FUNCTION
ZIP_EN (PAD 55)
CB/ZI (PAD 31)
0
ZI
1
CB
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