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参数资料
| 型号： | RDC-19222S-312T |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC44 |
| 封装： | PLASTIC, J LEAD PACKAGE-44 |
| 文件页数： | 14/20页 |
| 文件大小： | 266K |
| 代理商： | RDC-19222S-312T |
3
THEORY OF OPERATION
The RDC-19220/2S series of converter is a single CMOS cus-
tom monolithic chip. It is implemented using the latest IC tech-
nology which merges precision analog circuitry with digital logic
to form a complete high-performance tracking resolver-to-digital
converter. For user flexibility and convenience, the converter
bandwidth, dynamics, and velocity scaling are externally set with
passive components.
Figure 1 is the Functional Block Diagram of RDC-19220/2S.
The converter operates with ±5 V dc power supplies. Analog sig-
nals are referenced to analog ground, which is at ground poten-
tial. The converter is made up of two main sections; a converter
and a digital interface. The converter front-end consists of sine
and cosine differential input amplifiers. These inputs are protect-
ed to ±25 V with 2 k
resistors and diode clamps to the ±5 V dc
supplies. These amplifiers feed the high accuracy Control
Transformer (CT). Its other input is the 16-bit digital angle
φ. Its
output is an analog error angle, or difference angle, between the
two inputs. The CT performs the ratiometric trigonometric com-
putation of SIN
θCOSφ - COSθSINφ = SIN(θ-φ) using amplifiers,
switches, logic and capacitors in precision ratios.
Note: The transfer function of the CT is normally trigonometric,
but in LVDT mode the transfer function is triangular (linear) and
could thereby convert any linear transducer output.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In this converter ratioed capacitors are
used in the CT, instead of the more conventional precision
ratioed resistors. Capacitors used as computing elements with
op-amps need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate (67 kHz) to
eliminate this drifting and at the same time to cancel out the op-
amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage-
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which, togeth-
er with the velocity integrator, forms a type II servo feedback
loop. A lead in the frequency response is introduced to stabilize
the loop and another lag at higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
The settings of the various error processor gains and break fre-
quencies are done with external resistors and capacitors so that
the converter loop dynamics can be easily controlled by the user.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and its Bode Plots
(open and closed loop). These are shown in FIGURES 2, 3, and 4.
The open loop transfer function is as follows:
S
A2
+1
B
(
)
Open Loop Transfer Function =
S
S2
+1
10B
(
)
where A is the gain coefficient and A2 = A1A2
and B is the frequency of lead compensation
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT+Error
Amp+Demod with 2 Vrms input)
CSFS
- Integrator gain =
volts per second per volt
1.1CBW
1
- VCO Gain =
LSBs per second per volt
1.25 RvCvco
where:
Cs = 10 pF
Fs = 70 kHz when Rs = 30 k
Fs = 100 kHz when Rs = 20 k
Fs = 125 kHz when Rs = 15 k
Cvco = 50 pF
RV, RB, and CBW are selected by the user to set velocity scaling
and bandwidth.
GAIN
11 mV/LSB
16 BIT
UP/DOWN
COUNTER
R1
VCO
RV
RB CBW
C
/10
BW
VEL
-VCO
H = 1
-VSUM
VEL
C F
S S
CT
+
-
RESOLVER
INPUT
(
θ)
RS
50 pf
CVCO
DIGITAL
OUTPUT
(
φ)
DEMOD
±1.25 V
THRESHOLD
1
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
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