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参数资料
| 型号： | REJ03C0098_R1LV0408C |
| 厂商： | Hitachi,Ltd. |
| 英文描述： | Wide Temperature Range Version 4M SRAM (512-kword 】 8-bit) |
| 中文描述： | 宽温版本4分的SRAM（512 - KWord的】8位） |
| 文件页数： | 12/14页 |
| 文件大小： | 94K |
| 代理商： | REJ03C0098_R1LV0408C |
R1LV0408C-I Series
Rev.2.00, May.25.2004, page 12 of 12
Low V
CC
Data Retention Characteristics
(Ta =
40 to +85
°
C)
Parameter
Symbol Min Typ
Max Unit Test conditions
*
3
V
CC
for data retention
Data
retention
current
V
DR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
t
CDR
t
R
2.0
0
t
RC
*
4
10
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
ns
CS#
≥
V
CC
0.2 V, Vin
≥
0 V
V
CC
= 3.0 V, Vin
≥
0 V
CS#
≥
V
CC
0.2 V
to +85
°
C
to +70
°
C
to +40
°
C
to +25
°
C
to +85
°
C
to +70
°
C
to +40
°
C
to +25
°
C
0.7
*
2
3
0.5
*
1
3
0.7
*
2
10
0.5
*
1
10
8
5SI
20
16
7LI
Chip deselect to data retention time
See retention waveform
Operation recovery time
Notes: 1. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and specified loading, and not guaranteed.
2. Typical values are at V
CC
= 3.0 V, Ta = +40
°
C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. t
RC
= read cycle time.
ns
Low V
CC
Data Retention Timing Waveform
(CS# Controlled)
V
CC
2.7 V
2.2 V
V
DR
0 V
CS#
t
CDR
t
R
CS#
≥
V
CC
– 0.2 V
Data retention mode
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