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参数资料
| 型号： | RS5C316B-E2 |
| 厂商： | RICOH COMPANY LTD |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封装： | 0.65 MM PITCH, SSOP-8 |
| 文件页数： | 5/38页 |
| 文件大小： | 288K |
| 代理商： | RS5C316B-E2 |
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RS5C316A/B
9
2.1-2 (BSY)
When the BSY bit is 1, the clock and calendar counter are being updated. Consequently, write operation should
be performed for the counters when the BSY bit is 0. Meanwhile, read operation is normally performed for the
counters when the BSY bit is 0, but can be performed without checking the BSY bit as long as appropriate software
is provided for preventing read errors. (Refer to 13. Typical Software-based Operations.) The BSY bit is set to 1 in
the following three cases:
2.1-3 (WTEN)
The WTEN bit should be set to 0 to check that the BSY bit is 0 when performing read and write operations for
the clock and calendar counters. For read operation, the WTEN bit may be left as 1 without checking the BSY bit as
long as appropriate measures such as read repetition are provided for preventing read errors. The WTEN bit
should be set to 1 after completing read and write operations, or will automatically be set to 1 by switching the CE
pin to the low level. If 1-second digit carry occurs when the WTEN bit is 0, a second digit increment by 1 occurs
when the WTEN bit is set to 1. There may be a possibility causing a time delay when it takes 1/1024 second or
more to set WTEN bit from 0 to 1, Read data in state of WTEN=1 in such a case. (Refer to the item 13.3)
2.1-4 (XSTP)
The XSTP bit senses the oscillator halt. When the CE pin is held at the low level, the XSTP bit is set to 1 once
the crystal oscillator is stopped after initial power-on or supply voltage drop and left to be 1 after it is restarted.
When the CE pin is held at the high level, the XSTP bit is left as it was when the CE pin was held at the low level
without checking oscillation stop. As such, the XSTP bit can be used to validate clock and calendar count data after
power-on or supply voltage drop. The XSTP bit is set to 0 when any data is written to the control register 1 (at Eh)
with ordinary oscillation.
2.1-5 (ALFG)
The ALFG bit can be set to 1 when the ALE bit set to 1 with alarm interruption (INTR=L).
MAX.122.1
s
Setting of the
ADJ bit to 1
Completion of second
digit adjustment
(I) Adjustment of second digits
by
±30 second
(II) Second digits increment by 1
(Subject to 1-sec digit carry when
the WTEN bit is switched from 0 to 1)
(III) Ordinary 1-sec digit carry
MAX.91.6
s
Setting of the
WTEN bit to 1
End of second digit
increment by 1
91.6
s
End of second digit carry pulse
Matched alarm
register
Matched alarm
register
ALFG is written to 0
Matched alarm
register
ALFG
INTR
相关PDF资料 |
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| RS5C317B-E1 | 0 TIMER(S), REAL TIME CLOCK, PDSO14 |
| RS5C317B-E2 | 0 TIMER(S), REAL TIME CLOCK, PDSO14 |
| RS5C321A-E1 | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| RS5C321B-E1 | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RS5C317A | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:ULTRA-COMPACT HIGH PERFORMANCE SERIAL REAL-TIME CLOCK ICs |
| RS5C317A/B | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:real-time clock ICs |
| RS5C317B | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:ULTRA-COMPACT HIGH PERFORMANCE SERIAL REAL-TIME CLOCK ICs |
| RS5C321A | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:ULTRA-COMPACT SERIAL REAL-TIME CLOCK ICs WITH 32.768kHz |
| RS5C321A/B | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:real-time clock ICs |
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