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参数资料
| 型号： | RXM-900-HP3-SPS |
| 厂商： | Linx Technologies Inc |
| 文件页数： | 6/13页 |
| 文件大小： | 0K |
| 描述： | RECEIVER RF 902-928MHZ 8P/100S |
| 产品变化通告： | Internal Component Change 25/Aug/2011 |
| 标准包装： | 10 |
| 系列： | HP3 |
| 频率： | 902MHz ~ 928MHz |
| 灵敏度： | -100dBm |
| 数据传输率 - 最大： | 56 kbps |
| 调制或协议： | FM，FSK |
| 应用： | 家庭/工业自动化，远程访问，安全警报 |
| 电流 - 接收： | 18mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 特点： | 多通道，模拟和数字数据 |
| 电源电压： | 2.8 V ~ 13 V |
| 工作温度： | -30°C ~ 85°C |
| 封装/外壳： | 18-SMD 模块 |
| 供应商设备封装： | 18-SIP |
| 包装： | 管件 |
| 其它名称： | Q3400415 |
CHANNEL SELECTION
SERIAL CHANNEL SELECTION TABLE
Parallel Selection
All HP3 receiver models feature eight
parallel selectable channels. Parallel
Mode is selected by grounding the
MODE line. In this mode, channel
CS2
0
0
0
0
1
1
CS1
0
0
1
1
0
0
CS0
0
1
0
1
0
1
Channel
0
1
2
3
4
5
Frequency
903.37
906.37
907.87
909.37
912.37
915.37
CHANNEL TX FREQUENCY
0 902.62
1 902.87
2 903.12
3 903.37
4 903.62
RX LO
867.92
868.17
868.42
868.67
868.92
CHANNEL
51
52
53
54
55
TX FREQUENCY
915.37
915.62
915.87
916.12
916.37
RX LO
880.67
880.92
881.17
881.42
881.67
selection is determined by the logic
states of pins CS0, CS1, and CS2, as
1 1 0 6 919.87
1 1 1 7 921.37
shown in the adjacent table. A ‘0’ Table 2: Parallel Channel Selection Table
represents ground and a ‘1’ the positive supply. The on-board microprocessor
performs all PLL loading functions, eliminating external programming and
allowing channel selection via DIP switches or a product’s processor.
Serial Selection
In addition to the Parallel Mode, PS versions of the HP3 also feature 100 serially
selectable channels. The Serial Mode is entered when the MODE line is left open
or held high. In this condition, CS1 and CS2 become a synchronous serial port,
with CS1 serving as the clock line and CS2 as the data line. The module is easily
programmed by sending and latching the binary number (0 to 100) of the desired
channel (see the adjacent Serial Channel Selection Table). With no additional
effort, the module’s microprocessor handles the complex PLL loading functions.
5 903.87
6 904.12
7 904.37
8 904.62
9 904.87
10 905.12
11 905.37
12 905.62
13 905.87
14 906.12
15 906.37
16 906.62
17 906.87
18 907.12
19 907.37
20 907.62
869.17
869.42
869.67
869.92
870.17
870.42
870.67
870.92
871.17
871.42
871.67
871.92
872.17
872.42
872.67
872.92
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
916.62
916.87
917.12
917.37
917.62
917.87
918.12
918.37
918.62
918.87
919.12
919.37
919.62
919.87
920.12
920.37
881.92
882.17
882.42
882.67
882.92
883.17
883.42
883.67
883.92
884.17
884.42
884.67
884.92
885.17
885.42
885.67
straightforward; however,
Loading is initiated by
taking the clock line high
and the data line low as
8μs
The Serial Mode is
Note 2
Data
minimum timings and bit
Note 1
order must be followed. Clock
T0
1ms
shown. The eight-bit 25μs
T1
Variable Data
1 2 3 4 5 6 7 8
T3
T2 5μs
5μs
T4
Note 3
21 907.87
22 908.12
23 908.37
24 908.62
25 908.87
26 909.12
27 909.37
28 909.62
29 909.87
873.17
873.42
873.67
873.92
874.17
874.42
874.67
874.92
875.17
72
73
74
75
76
77
78
79
80
920.62
920.87
921.12
921.37
921.62
921.87
922.12
922.37
922.62
885.92
886.17
886.42
886.67
886.92
887.17
887.42
887.67
887.92
channel number is then
1) Loading begins when clock line is high and data line is taken low
30 910.12
875.42
81
922.87
888.17
clocked-in one bit at a 2) Ensure that edge is fully risen prior to high-clock transition
31 910.37
875.67
82
923.12
888.42
time, with the LSB first.
3) Both lines high triggers automatic latch
32 910.62
875.92
83
923.37
888.67
(T0) Time between packets or prior to data startup ................................1mS
(T1) Data-LO / Clock-HI to Data-LO / Clock-LO .......................................25μS
(T2) Clock-LO to Clock-HI ...........................................................................5μS
(T3) Clock-HI to Clock-LO ...........................................................................8μS
(T4) Data-HI / Clock-HI .................................................................................5μS
Total Packet Time ......................................................................................157μS
Figure 13: PLL Serial Data Timing
min.
min.
min.
min.
min.
min.
33 910.87
34 911.12
35 911.37
36 911.62
37 911.87
38 912.12
39 912.37
40 912.62
41 912.87
876.17
876.42
876.67
876.92
877.17
877.42
877.67
877.92
878.17
84
85
86
87
88
89
90
91
92
923.62
923.87
924.12
924.37
924.62
924.87
925.12
925.37
925.62
888.92
889.17
889.42
889.67
889.92
890.17
890.42
890.67
890.92
There is no maximum time for this process, only the minimum times that must be
observed. After the eighth bit, both the clock and data lines should be taken high
to trigger the automatic data latch. A typical software routine can complete the
loading sequence in under 200uS. Sample code is available on the Linx website.
NOTE: When the module is powered up in the Serial Mode, it will default to channel 50 until changed
by user software. This allows testing apart from external programming and prevents out-of-band
operation. When programmed properly, the dwell time on this default channel can be less than 200uS.
Channel 50 is not counted as a usable channel since data errors may occur as transmitters also default
to channel 50 on startup. If a loading error occurs, such as a channel number >100 or a timing problem,
42 913.12
43 913.37
44 913.62
45 913.87
46 914.12
47 914.37
48 914.62
49 914.87
50* 915.12
878.42
878.67
878.92
879.17
879.42
879.67
879.92
880.17
880.42
93
94
95
96
97
98
99
100
925.87
926.12
926.37
926.62
926.87
927.12
927.37
927.62
= Also available in Parallel
891.17
891.42
891.67
891.92
892.17
892.42
892.67
892.92
Mode
the receiver will default to serial channel 0. This is useful for debugging as it verifies serial port activity.
Page 10
*See NOTE on previous page.
Page 11
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