参数资料
型号: S1C33L05
元件分类: 微控制器/微处理器
英文描述: RISC MICROCONTROLLER, PQFP176
封装: 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP21-176
文件页数: 2/8页
文件大小: 81K
代理商: S1C33L05
2
S1C33L05
Timers ....................................................... 8-bit timer
6 channels
16-bit timer
6 channels
Watchdog timer
1 channel (16-bit timer 0's function)
Clock timer
1 channel (with alarm function)
Serial interface .......................................... 4 channels
Clock-synchronous system, asynchronous system and IrDA 1.0
interface are selectable.
Ch.0 is selectable between a built-in buffer type (a 4-byte receive-
data buffer and a 2-byte transmit-data buffer) and no buffer type.
A/D converter ............................................ 10 bits
× 5 channels
LCD controller ........................................... 4 or 8-bit monochrome/color LCD interface
Panels supported
- Single-panel, single drive passive display
- 4/8-bit monochrome LCD interface
- 4/8-bit color LCD interface
Display modes
- 16-bpp mode: 64K colors or 64-level gray scale display
- 12-bpp mode: 4096 colors or 16-level gray scale display
- 8-bpp mode:
256 colors or 64-level gray scale display
- 4-bpp mode:
16 colors or 16-level gray scale display
- 2-bpp mode:
4 colors or 4-level gray scale display
- 1-bpp mode:
2 colors or 2-level gray scale display
A 256 × 3 × 6-bit Look-Up Table (256K-color palette) is pro-
vided for displaying 256 colors simultaneously. The LUT can
be bypassed to send display data from VRAM directly to the
LCD.
Gray scale display uses FRM (Frame Rate Modulation) and
dithering.
Resolution (programmable)
Typical resolutions when only the internal VRAM is used:
- 320
× 240 pixels in 4-bpp mode
- 160
× 240 pixels in 8-bpp mode
- 160
× 160 pixels in 12-bpp mode
Typical resolutions when an external VRAM is used via the
UMA:
- 320
× 240 pixels in 8-bpp mode
- 320
× 240 pixels in 16-bpp mode
SDRAM controller ..................................... 48 MHz synchronous clock max.
Supports up to 256M-bit (32MB) SDRAM with 16-bit data width.
16-stage IQB (32-byte Instruction Queue Buffer) and 2-stage
DQB (4-byte Data Queue Buffer) are provided.
Allows LCDC DMA controller to access SDRAM directly as an
external VRAM.
MMC (SPI mode) interface ....................... 1 channel
Supports 1 to 16-bit serial data transfer in master mode.
Compatible with MMC.
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