参数资料
型号: S1C33L05
元件分类: 微控制器/微处理器
英文描述: RISC MICROCONTROLLER, PQFP176
封装: 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP21-176
文件页数: 3/8页
文件大小: 81K
代理商: S1C33L05
3
S1C33L05
NAND flash interface ................................ Generates the #SMWE and #SMRE signals using the BCU sig-
nals to interface directly with SmartMedia cards or NAND flash
memories.
Supports 8/16-bit Nand flash devices. Also the Nand flash booting
function and the ECC function when a Nand flash is read/written
are supported.
Sequential ROM interface ........................ Supports MX23L12813 (manufactured by Macronix International
Co., Ltd.).
Generates the SQUALE, SQLALE and #SQRD signals using the
BCU signals to interface directly with the sequential mask ROM.
USB1.1 function controller ........................ Endpoint: EP0, EPa, EPb, EPc, EPd (4 channels);
FIFO: 1,024 bytes
DMA controller .......................................... High-speed DMA
4 channels
High-speed DMA Ch. 3 has been reserved
for the internal USB1.1 function controller.
Intelligent DMA
128 channels
Interrupt controller .................................... Possible to invoke DMA
Input interrupt
10 types (programmable)
DMA controller interrupt
5 types
16-bit programmable timer interrupt
12 types
8-bit programmable timer interrupt
6 types
Serial interface interrupt
15 types
A/D converter interrupt
1 type
Clock timer interrupt
1 type
LCD controller interrupt
1 type
SPI interrupt
1 type
USB function controller interrupt
1 type
General-purpose input and output ports ... Shared with the I/O pins for internal peripheral circuits
Input port
9 bits (max.)
I/O port
69 bits (max.)
The K54 and K65–K67 pins are not available in the S1C33L05.
Two LED direct output (8 mA) ports (P27 and P26) are avail-
able.
The number of the ports varies depending on the peripheral
functions used.
● External bus interface
BCU (bus control unit) built-in
26-bit address bus (internal 28-bit processing)
16-bit data bus (Data size is selectable from 8 bits and 16 bits in each area.)
Little/big-endian memory access; endian type may be set in each area.
Memory mapped I/O
Chip enable and wait control circuits built-in
Supports burst ROM.
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