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参数资料
| 型号： | S1R72V27B05 |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封装： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件页数： | 14/42页 |
| 文件大小： | 426K |
| 代理商： | S1R72V27B05 |
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6. Terminal Functions
16
EPSON
S1R72V27 Data Sheet (Rev. 1.00)
CPU I/F
QFP
Pin
BGA5
Ball
BGA8
Ball
Name
I/O
RESET
Terminal
type
Terminal description
Bus Mode
Strobe Mode
BE Mode
6
D1
XRESET
IN
-
Schmitt
Reset signal
54
D8
D9
CLKIN
IN
-
External clock input
23
G3
H4
XRD
IN
-
Read/strobe
25
H3
XWRL
(XWR)
IN
-
Write/strobe (lower)
Write/strobe
24
F3
J3
XWRH
(XBEH)
IN
-
Write/strobe
(upper)
High-byte enable
22
H2
G4
XCS
IN
-
Schmitt
Chip select signal
21
E3
H2
XINT
OUT
High
2mA
(Tri-state)
Interrupt output signal
26
G4
J4
XDREQ
OUT
High
2mA
DMA request
27
F4
G5
XDACK
IN
-
DMA acknowledge
7
D2
C4
XBEL
IN
-
Set to High or
Low
Low-byte enable
8
C4
C5
CA1
IN
-
9
E1
CA2
IN
-
10
C5
D3
CA3
IN
-
11
E2
E3
CA4
IN
-
14
D3
F2
CA5
IN
-
15
G1
G2
CA6
IN
-
16
F1
G1
CA7
IN
-
17
F2
F3
CA8
IN
-
CPU bus address
28
H4
G6
CD0
BI
Hi-Z
2mA
29
G5
H5
CD1
BI
Hi-Z
2mA
30
H5
J5
CD2
BI
Hi-Z
2mA
34
F5
J6
CD3
BI
Hi-Z
2mA
35
E6
G7
CD4
BI
Hi-Z
2mA
36
H6
J7
CD5
BI
Hi-Z
2mA
37
G6
H7
CD6
BI
Hi-Z
2mA
38
F6
F7
CD7
BI
Hi-Z
2mA
39
H7
G8
CD8
BI
Hi-Z
2mA
43
G8
F8
CD9
BI
Hi-Z
2mA
44
F7
G9
CD10
BI
Hi-Z
2mA
47
E7
F9
CD11
BI
Hi-Z
2mA
48
F8
D7
CD12
BI
Hi-Z
2mA
49
D6
E8
CD13
BI
Hi-Z
2mA
50
E8
E9
CD14
BI
Hi-Z
2mA
51
C6
D8
CD15
BI
Hi-Z
2mA
CPU data bus
The XINT terminal can be set to 1/0 or Hi-Z/0 mode, depending on register settings. Note, however, that it cannot be
pulled up with a voltage exceeding the rated value even in Hi-Z/0 mode, since it is not an open drain.
The clock inputs from the crystal oscillator and CLKIN for XI and XO are used exclusively by the register settings. Fix
CLKIN at Low when using XI and XO.
PD: Pull Down
PU: Pull Up
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