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参数资料
| 型号： | S29CL016J0MFAI113 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件页数： | 78/78页 |
| 文件大小： | 1825K |
| 代理商： | S29CL016J0MFAI113 |
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September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
7
Pr el im i n a r y
2
Input/Output Descriptions and Logic Symbols
Table identifies the input and output package connections provided on the device.
Symbol
Type
Description
A19-A0
Input
Address lines for S29CD-J and S29CL-J (A18-A0 for 16Mb and A19-A0 for 32Mb).
A9 supports 12V autoselect input.
DQ31-DQ0
I/O
Data input/output
CE#
Input
Chip Enable.
This signal is asynchronous relative to CLK for the burst mode.
OE#
Input
Output Enable.
This signal is asynchronous relative to CLK for the burst mode.
WE#
Input
Write Enable
VCC
Supply
Device Power Supply.
This signal is asynchronous relative to CLK for the burst mode.
VIO
Input
VersatileI/OTM Input.
VSS
I/O
Ground
NC
No Connect
Not connected internally
RY/BY#
Output
Ready/Busy output and open drain which require a external pull up resistor.
When RY/BY# = VOH, the device is ready to accept read operations and commands.
When RY/BY# = VOL, the device is either executing an embedded algorithm or the
device is executing a hardware reset operation.
CLK
Input
Clock Input that can be tied to the system or microprocessor clock and provides the
fundamental timing and internal operating frequency.
AVD #
Input
Load Burst Address input.
Indicates that the valid address is present on the address inputs.
IND#
Output
End of burst indicator for finite bursts only.
IND is low when the last word in the burst sequence is at the data outputs.
WAIT#
Output
Provides data valid feedback only when the burst length is set to continuous.
WP#
Input
Write Protect Input.
At VIL, disables program and erase functions in two outermost sectors of the large
bank.
ACC
Input
Acceleration input.
At VHH, accelerates erasing and programming.
When not used for acceleration, ACC = VSS to VCC.
RESET#
Input
Hardware Reset.
相关PDF资料 |
PDF描述 |
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| S29CL016J0PQFI102 | 512K X 32 FLASH 3.3V PROM, 54 ns, PQFP80 |
| S29CL016J0MFAM100 | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL016J0PFFM102 | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL016J1JFFM112 | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CD032J1JFAN110 | 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29CL016J0MQFM030 | 制造商:Spansion 功能描述: |
| S29CL016J0MQFM030P | 制造商:Spansion 功能描述:32M (4MX8/2MX16) 3V REG, MIRRORBIT, TOP, FBGA48, IND - Trays |
| S29CL016J1JFAI020 | 制造商:Spansion 功能描述:16 - Tape and Reel |
| S29CL032J0MFAI030 | 制造商:Spansion 功能描述:32MBIT FLASH - Trays |
| S29CL032J0PQFM010 | 制造商:Spansion 功能描述: 制造商:Spansion 功能描述:32MBIT FLASH - Tape and Reel |
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