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参数资料
| 型号： | S29GL032M10BFIR20 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | T528 Series - I, M, Z Case Sizes - Face Down Termination Tantalum Surface Mount Capacitor; Capacitance [nom]: 220uF; Working Voltage (Vdc)[max]: 4V; Capacitance Tolerance: +/-20%; Dielectric: Tantalum, Solid; ESR: 9.0mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-17; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 1.7mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 1,000; Features: Face Down Termination |
| 中文描述： | 2M X 16 FLASH 3V PROM, 100 ns, PBGA64 |
| 封装： | 13 X 11 MM, LEAD FREE, FORTIFIED BGA-64 |
| 文件页数： | 23/158页 |
| 文件大小： | 4695K |
| 代理商： | S29GL032M10BFIR20 |
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August 4, 2004 S29GLxxxM_00_B1_E
S29GLxxxM MirrorBitTM Flash Family
119
Da ta shee t
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is,
the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or
is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are re-
quired for sector and mode information. Refer to Table 37 to compare outputs for DQ2 and DQ6.
8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm.
See also the RY/BY#: Ready/Busy# subsection. 20 shows the toggle bit timing diagram. 21 shows the differences
between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must
read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second read, the system would compare
the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program
or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then de-
termine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went
high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation.
If it is still toggling, the device did not completed the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone
high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining
the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the algorithm when it returns to determine the status of the
operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device
halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset command to return the device to the reading the array (or to
erase-suspend-read if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure
has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected
for erasure, the entire time-out also applies after each additional sector erase command. When the time-out pe-
riod is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from
the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase
Command Sequence section.
相关PDF资料 |
PDF描述 |
|---|---|
| S29GL032M10BFIR22 | T528 Series - I, M, Z Case Sizes - Face Down Termination Tantalum Surface Mount Capacitor; Capacitance [nom]: 220uF; Working Voltage (Vdc)[max]: 4V; Capacitance Tolerance: +/-20%; Dielectric: Tantalum, Solid; ESR: 12mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-17; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 1.7mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 1,000; Features: Face Down Termination |
| S29GL032M10BFIR23 | T528 Series - I, M, Z Case Sizes - Face Down Termination Tantalum Surface Mount Capacitor; Capacitance [nom]: 220uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Tantalum, Solid; ESR: 9.0mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-17; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 1.7mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 1,000; Features: Face Down Termination |
| S29GL032M10BFIR12 | MirrorBit Flash Family |
| S29GL032M10BFIR13 | MirrorBit Flash Family |
| S29GL032M10BFIR30 | T528 Series - I, M, Z Case Sizes - Face Down Termination Tantalum Surface Mount Capacitor; Capacitance [nom]: 220uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Tantalum, Solid; ESR: 12mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-17; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 1.7mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 1,000; Features: Face Down Termination |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29GL032M10BFIR22 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10BFIR23 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10BFIR30 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL032M10BFIR32 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL032M10BFIR33 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
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