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参数资料
| 型号： | S3P9664-AM |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP24 |
| 封装： | 0.300 INCH, SDIP-24 |
| 文件页数： | 23/148页 |
| 文件大小： | 784K |
| 代理商： | S3P9664-AM |
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UNIVERSAL SERIAL BUS
S3C9664/P9664 (Preliminary Spec)
13-14
CONTROL ENDPOINT FIFO REGISTER (EP0FIFO)
This register is bi-directional, 8 byte depth FIFO used to transfer Control Endpoint data. EP0FIFO is located at
address F4H and is read/write addressable.
Initially, the direction of the FIFO, is from the Host to the MCU. After a setup token is received for a control
transfer, that is, after MCU unload the setup token bytes, and clears OUT_PKT_RDY, the direction of FIFO is
changed automatically from MCU to the Host.
INTERRUPT ENDPOINT 1 FIFO REGISTER (EP1FIFO)
EP1FIFO is an bi-direction 8-byte depth FIFO used to transfer data from the MCU to the Host or from the Host to
the MCU. MCU writes data to this register, and when finished set IN_PKT_RDY. Meanwhile, when USB recieves
valid data through this register , it sets OUT_PKT_RDY , after MCU unload Data bytes, and clears
OUT_PKT_RDY , This register is located at address F5H.
INTERRUPT ENDPOINT 2 FIFO REGISTER (EP2FIFO)
EP2FIFO is an bi-direction 8-byte depth FIFO used to transfer data from the MCU to the Host or from the Host to
the MCU. MCU writes data to this register, and when finished set IN_PKT_RDY. Meanwhile, when USB recieves
valid data through this register , it sets OUT_PKT_RDY , after MCU unload Data bytes, and clears
OUT_PKT_RDY , This register is located at address FAH.
USB INTERRUPT PENDING REGISTER (USBPND)
USBPND register has the interrupt bits for endpoints and power management. This register is cleared once read
by MCU. While any one of the bits is set, an interrupt is generated. USBPND is located at address F6H.
Bit7–6 Not used
Bit5
USB_RST_PND: This bit is set, when USB reset signal is received.
Bit4
ENDPT2_PND: This bit is set, when Endpoint 2 needs to be received.
Bit3
RESUME_PND: While in suspend mode, if resume signaling is received this bit gets set.
Bit2
SUSPEND_PND: This bit is set, when suspend signaling is received.
Bit1
ENDPT1_PND: This bit is set, when Endpoint 1 needs to be serviced.
Bit0
ENDPT0_PND: This bit is set, when Endpoint 0 needs to be serviced. It is set under any one of the
following conditions:
— OUT_PKT_RDY is set.
— IN_PKT_RDY gets cleared.
— SENT_STALL gets set.
— DATA_END gets cleared.
— SETUP_END gets set.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S3P9688 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:8-bit single-chip CMOS microcontrollers |
| S3PDB100 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:Three Phase Rectifier Modules |
| S3PDB100N08 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:Three Phase Rectifier Modules |
| S3PDB100N12 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:Three Phase Rectifier Modules |
| S3PDB100N14 | 制造商:SIRECTIFIER 制造商全称:Sirectifier Semiconductors 功能描述:Three Phase Rectifier Modules |
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