Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
7-9
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
Byte
Binary
Offset
Length
Value
Description
Example
68h
8
not used
8 DUP(?)
70h
4
[Expansion
(see Section 4.12)
ROM base addr.]
(example shows 32K bytes)
FFFF8001h
74h
8
not used
8 DUP(?)
7Ch
1
[Interrupt line]
(see Section 4.13)
0Ch
7Dh
1
[Interrupt pin]
(see Section 4.14)
01h
7Eh
1
[Min-Grant]
(see Section 4.15)
00h
7Fh
1
[Max_lat]
(see Section 4.16)
00h
80h —
application specific
(1FFh), or
(2FFh), or
(3FFh), etc.
Byte checksum, location dependent on value for length field at offset 0002h.
Table 7-2. PC Compatible Expansion ROM (Continued)
A 16-bit pointer at location 18h of the PC expansion
ROM identifies the start offset of the PCI data struc-
ture. The PCI data structure is shown in Table 7-3
and contains various vendor, product, and program
evolutions. If a valid external nv memory is identified
by the S5933 (as described in Sections 7.2 and 7.3),
the PCI data structure is used to configure the
S5933. The PCI data structure is not necessary for
this device to operate. If no external nv memory is
implemented, the S5933 boots with the default con-
figuration values described in Chapter 4.
Byte
Binary
Offset
Length
Value
Description
0h
4
‘PCIR’
Signature, the ASCII string ‘PCIR’ where ‘P’ is at offset 0,
‘C’ at offset 1, and so on.
4h
2
var.
Vendor Identification
6h
2
var.
Device Identification
8h
2
var.
Pointer to Vital Product Data
Ah
2
var.
PCI Data Structure Length (starts with signature field)
Ch
1
var.
PCI Data Structure Revision (=0 for this definition)
Dh
3
var.
Class Code
10h
2
var.
Image Length
12h
2
var.
Revision Level
14h
1
var.
Code Type
15h
1
var.
Indicator (bit D7=1 signifies “last image”)
16h
2
0000h
Reserved
Table 7-3. PCI Data Structure
Note: If a serial BIOS ROM is used, the access time
for large serial devices should be considered, since it
may cause a lengthy system delay during initializa-
tion. For example, a 2-Kbyte serial device takes
about 1 second to be read. Many systems, even
when BIOS ROMs are ultimately shadowed into sys-
tem RAM, may read this memory space twice (once
to validate its size and checksum, and once to move
it into RAM). Execution directly from a serial BIOS
ROM, although possible, may be unacceptably slow.