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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
7-3
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
BiCMOS PECL CLOCK GENERATOR
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
7.0
INITIALIZATION
All PCI bus agents and bridges are required to imple-
ment PCI Configuration Registers. When multiple
PCI devices are present, these registers must be
unique to each device in the system. The specified
PCI procedure for uniquely selecting a device’s con-
figuration space involves a dedicated signal, called
IDSEL, connected to each motherboard PCI bus de-
vice and PCI slot (see Section 7.4).
The host executes configuration cycles after reset to
each device on the PCI bus. The configuration regis-
ters provide information on PCI agent operation and
memory or I/O space requirements. These allow the
PCI BIOS to enable the device and locate it within
system memory or I/O space.
After a PCI reset, the S5933 can be configured for a
specific application by downloading device setup in-
formation from an external non-volatile memory into
the device Configuration Registers. The S5933 can
also be used in a default configuration, with no external
boot device. Default states for the user-definable PCI
Configuration Registers are described in Chapter 4.
When using a non-volatile boot memory to customize
operation, 64 bytes are required for S5933 setup in-
formation. The rest of the boot device may be used to
implement an Expansion BIOS (Section 7.5), if de-
sired. Some of the setup information is used to initial-
ize the S5933 PCI Configuration Registers, other
information is not downloaded into registers, but is
used to define S5933 operation (FIFO interface,
Pass-Thru operation, etc.).
7.1
PCI RESET
Immediately following the assertion of the PCI RST#
signal, the Add-On reset output SYSRST# is as-
serted. Immediately following the deassertion of
RST#, SYSRST# is deasserted. The Add-On reset
output may be used to initialize state machines, reset
Add-On microprocessors, or reset other Add-On logic
devices.
All S5933 Operation Registers and Configuration
Registers are initialized to their default states at re-
set. The default values for the Configuration Regis-
ters may be overwritten with the contents of an
external nv boot memory during device initialization,
allowing a custom device configuration. This process
is described, in detail, in Sections 7.2 and 7.3. Con-
figuration accesses by the host CPU to the S5933
produce PCI bus wait states until one of the following
events occurs:
The S5933 identifies that there is no valid boot
memory (and default Configuration Register
values are used).
The S5933 finishes downloading all configura-
tion information from a valid boot memory.
7.2
LOADING FROM BYTE-WIDE NV MEMORIES
The SNV input on the S5933 indicates what type of
external boot-load device is present (if any). If SNV is
tied low, a byte-wide nv memory is assumed. In this
case, immediately after the PCI bus reset is
deasserted, the address 0040h is presented on the
nv memory interface address bus EA[15:0]. Eight PCI
clocks later (240 ns at 33 MHz), data is read from the
nv memory data bus EQ[7:0] and address 0041h is
presented. After an additional eight PCI clocks, data
is again read from EQ7:0. If both accesses read are
all ones (FFh), it implies an illegal Vendor ID value,
and the external nv memory is not valid or not
present. In this situation, the AMCC default configu-
ration values are used (see Chapter 4).
If either of the accesses to address 0040h and 0041h
contain zeros (not FFh), the next accesses are to
locations 0050h, 0051h, 0052h, and 0053h. At these
locations, the data must be C0h (or C1h or C2h),
FFh, E8h, and 10h, respectively, for the external nv
memory to be valid. Once a valid external nv memory
has been recognized, it is read, sequentially, from
location 0040h to 007Fh. The appropriate data is
loaded into the PCI Configuration Registers as de-
scribed in Chapter 4. Some of the boot device data is
not downloaded into Configuration Registers, but is
used to enable features and configure S5933 opera-
tion. Upon completion of this procedure, the boot-
load sequence terminates and PCI configuration
accesses to the S5933 are acknowledged with the
PCI Target Ready (TRDY#) output.
Table 7-1 lists the required nv memory contents for a
valid configuration nv memory device.