- 您现在的位置：买卖IC网 > PDF目录98071 > S6A0032 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 PDF资料下载
参数资料
| 型号： | S6A0032 |
| 元件分类： | 显示控制器 |
| 英文描述： | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| 封装： | DIE-138 |
| 文件页数： | 3/39页 |
| 文件大小： | 361K |
| 代理商： | S6A0032 |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
7
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
S6A0032 has two kinds of interface type with MPU: 4-bit bus or 8-bit bus. 4-bit bus and 8-bit bus is selected by the
DL bit in the instruction register, and 6800-series MPU or 8080-series MPU is selected by MI pin.
Table 4. Various Kinds of MPU Interface according to MI and DL Bit
MI
DL
CSB
RS
RW_WR
E_RD
DB0 to DB3
DB4 to DB7
8-bit (H)
CSB
RS
R/W
E
DB0 to DB3
DB4 to DB7
6800
series (H)
4-bit (L)
CSB
RS
R/W
E
-
DB4 to DB7
8-bit (H)
CSB
RS
WR
RD
DB0 to DB3
DB4 to DB7
8080
series (L)
4-bit (L)
CSB
RS
WR
RD
-
DB4 to DB7
NOTE: "-" - Don’t care ("High", "Low" or Open)
(H): fixed "High" (VDD)
(L): fixed "Low" (VSS)
MI: "High" = 6800-series MPU, "Low" = 8080-series MPU
DL: "High" = 8-bit mode, "Low" = 4-bit mode
CSB: "High" = chip is not selected, "Low" = chip is selected
RS: "High" = data register, "Low" = instruction register
RW_WR: read / write indicating signal in 6800 mode, active high signal for writing command in 8080 mode.
E_RD: Active low signal for writing command or high enable signal for reading command in 6800 mode,
low enable signal for reading command in 8080 mode.
Parallel Interface
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data
register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM. Target RAM is
selected by RAM address set instruction. The Instruction register (IR) is used only to store instruction code
transferred from MPU. To select DR or IR register, RS input pin is used.
During reading operation, 8-bit output data register (OR) is used. The output data register (OR) is used as temporary
data storage place for being read from DDRAM / CGRAM. Destination RAM is selected by RAM address set
instruction. After RAM address set, the first reading in the 8-bit bus mode (first and second reading in the 4-bit bus
mode) is a dummy cycle (figure 3, 4, 5, 6). The valid data comes from the second reading in the 8-bit bus mode (from
the 3rd reading in 4-bit bus mode). The dummy cycle makes the address counter (AC) indicate the correct address.
So it is recommended to set address before writing. The instruction read operation is supported for indicating
internal operation is being processed (Busy Flag).
In the 4-bit bus mode, it is needed to transfer 4-bit data (through DB4 to DB7) by two times. The high order bits (for
8-bit mode DB4 to DB7) are transferred before the low order bits (for 8-bit mode DB0 to DB3) in read and write
transaction. The DB0 to DB3 pins are floated in this 4-bit bus mode.
After RESETB operation, S6A0032 considers the first 4-bit data from MPU as the high order bits in the 4-bit bus
mode.
相关PDF资料 |
PDF描述 |
|---|---|
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
| S80960SA-16 | 32-BIT, 16 MHz, RISC PROCESSOR, PQFP80 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S6A0035 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:53 SEGMENT STATIC DRIVER |
| S6A0065 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:40 CH SEGMENT/COMMON DRIVER FOR DOT MATRIX LCD |
| S6A0065B01-Q08J | 制造商:Samsung Semiconductor 功能描述: |
| S6A0065B01-Q0RJ | 制造商:Samsung Semiconductor 功能描述:N/A - Trays |
| S6A0069 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD |
发布紧急采购，3分钟左右您将得到回复。