- 您现在的位置：买卖IC网 > PDF目录25624 > S80C32-25SHXXX:RD (ATMEL CORP) 8-BIT, 25 MHz, MICROCONTROLLER, PQCC44 PDF资料下载
参数资料
| 型号： | S80C32-25SHXXX:RD |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 33/109页 |
| 文件大小： | 10824K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页当前第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页
278
7593L–AVR–09/12
AT90USB64/128
RSTDT - Reset Data Toggle bit
Set to automatically clear the data toggle sequence:
For OUT endpoint: the next received packet will have the data toggle 0.
For IN endpoint: the next packet to be sent will have the data toggle 0.
Cleared by hardware instantaneously. The firmware does not have to wait that the bit is cleared.
Clearing by software has no effect.
2 - Reserved
The value read from these bits is always 0. Do not set these bits.
1 - Reserved
The value read from these bits is always 0. Do not set these bits.
0 - EPEN - Endpoint Enable bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be
enabled after a hardware or USB reset and participate in the device configuration.
Clear this bit to disable the endpoint. See Section 23.6, page 263 for more details.
7-6 - EPTYPE1:0 - Endpoint Type bits
Set this bit according to the endpoint configuration:
00b: Control10b: Bulk
01b: Isochronous11b: Interrupt
5-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
3-2 - Reserved for test purpose
The value read from these bits is always 0. Do not set these bits.
1 - Reserved
The value read from this bits is always 0. Do not set this bit.
0 - EPDIR - Endpoint Direction bit
Set to configure an IN direction for bulk, interrupt or isochronous endpoints.
Clear to configure an OUT direction for bulk, interrupt, isochronous or control endpoints.
Bit
7
6
543
21
0
EPTYPE1:0
-
EPDIR
UECFG0X
Read/write
R/W
R
RRRR
R/W
Initial value
0
000
00
0
相关PDF资料 |
PDF描述 |
|---|---|
| S80C52XXX-20:RD | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44 |
| S80C52XXX-36:RD | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQCC44 |
| MC80C32E-30:D | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| MR80C32E-20 | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
| MR80C32E-20 | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S80C32-30 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| S80C32-30R | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| S80C32-33 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| S-80C32-36 | 制造商:TEMIC 功能描述: |
| S80C32-36 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
发布紧急采购，3分钟左右您将得到回复。