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参数资料
| 型号： | SA56615-46D |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封装： | 1.50 MM, PLASTIC, SOT-23, SOT-25, SO-5 |
| 文件页数： | 9/23页 |
| 文件大小： | 244K |
| 代理商： | SA56615-46D |
Philips Semiconductors
Product data
SA56615-XX;
SA56616-XX
CMOS system reset with adjustable delay time
2003 Oct 15
17
TECHNICAL DISCUSSION
The SA56616-XX and SA56615-XX are CMOS devices designed to
monitor the system’s power source and provide a system reset
function in the event the supply voltage sags below an acceptable
level for the system to reliably operate. The SA56616-XX and
SA56615-XX generate a compatible reset signal for a wide variety
of microprocessors and logic systems. They can operate up to
10 volts. The series includes several versions providing high
precision reset threshold levels of 0.9, 1.8, 1.9, 2.0, 2.7, 2.8, 2.9,
3.0, 3.1, 4.2, 4.3, 4.4, 4.5, 4.6, and 4.7 V. The reset threshold
incorporates a typical hysteresis of (VS × 0.05) volts to prevent
erratic resets from being generated. The SA56616-XX and
SA56615-XX operate at very low supply currents, typically 1.2
A,
while offering high precision of threshold detection, typically
±2%.
They have an on-chip reset time delay which is adjusted by an
external capacitor.
The SA56616-XX and SA56615-XX offer different output options;
one or the other may be preferred depending on the system criteria.
The SA56616-XX (Figure 2) incorporates an active push-pull,
Totem-pole output topology comprised of complimentary P-channel
and N-channel FETs. A P-channel is on the high supply side and
when ON pulls the output to or near the VDD supply voltage from
which output source current can be obtained. A complimentary
N-channel FET is on the low supply side or ground side, and
actively pulls the output LOW or to ground with the capability of
sinking current into the output. When connecting the SA56616-XX to
a system, the user should be aware of the effect of supplying source
current from the output of the SA56616-XX on the system. The
SA56615-XX (Figure 1) incorporates a low side N-channel
open-drain topology, which requires an external pull-up to VDD.
Though this may be regarded as a disadvantage, it is an advantage
in many sensitive applications because the open-drain output can
not source reset current to a microprocessor when both are
operated from a common supply. For this reason, the SA56615-XX
offers a safe interconnect to a wide variety of microprocessors.
Figure 73 and Figure 74 are the functional block diagrams of the
SA56615-XX and SA56616-XX, respectively. The only difference
between them is the output configuration. The internal reference is
typically 0.8 V over the operating temperature range. The reference
voltage is connected to the non-inverting input of the threshold
comparator while the inverting input monitors the supply voltage
through a resistor divider network made up of R1, R2, and R3. The
output threshold comparator drives the time delay/inverting amplifier
network and, in turn, the totem-pole output stage.
When the supply voltage sags to the threshold detection voltage, the
resistor divider network supplies a voltage to the inverting input of
the threshold comparator which is less than VREF, causing the
output of the comparator to go HIGH. This switches the N-channel
FET (M3) to an active ON state, pulling its output (drain) to a low
voltage state. The output of M3 is connected to the internal resistor,
RD, the time delay pin CD, and the input of the inverting amplifier.
The output level of the CD pin will rise to the level of VTCD by the
time constant formed by internal RD to VDD and external CD to
ground. The output of the inverting amplifier will then be pulled to a
LOW state. This causes the high side FET M1 of the totem-pole
output stage to turn off while simultaneously turning the low side
N-channel FET M2 to an active ON state, pulling the output to a low
voltage state.
The device adheres to true input/output logic protocol. The output
goes to a low voltage state when the input is LOW (below VSL) and
the output goes HIGH when the input is HIGH (above VSH).
The low side N-channel FET (M4) establishes threshold hysteresis
by turning ON whenever the threshold comparator output goes to a
HIGH state (when VDD sags to or below the VSL level). With M4 in the
ON state, additional current flows through resistors R1 and R2 which
causes the inverting input of the threshold comparator to be pulled
even lower. For the comparator to reverse its output polarity and turn
OFF M4, the VDD source voltage must overcome this additional
pull-down voltage on the comparator’s inverting input. The differential
voltage required to do this establishes the hysteresis voltage of the
sensed threshold voltage. Typically, this is (VS × 0.5) volts.
When the VDD voltage sags and is at or below the Detection
Threshold (VSL), the device will assert a Reset Low output at or very
near ground potential. As the VDD voltage rises from (VDD < VSL) to
VSH or higher, the reset is released and the output follows VDD.
Conversely, decreases in VDD from (VDD > VSL) to VSL or lower
cause the output to be pulled to ground.
Hysteresis Voltage = Release Voltage – Detection Threshold Voltage
Vhys = VSH – VSL
where:
VSH = VSL + Vhys = VREF(R1 + R2)/R2
VSL = VREF(R1 + R2 + R3)/(R2 +R3)
When VDD drops below the minimum operating voltage, typically
less than 0.95 volts, the output is undefined and output reset low
assertion is not guaranteed. At this level of VDD the output will try to
rise to VDD.
The VREF voltage is typically 0.8 V. The devices are fabricated using
a high resistance CMOS process and utilize high resistance R1, R2,
and R3 values requiring very small amounts of current. This
combination achieves very efficient low power performance over the
full temperature.
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