参数资料
型号: SAB-C167CS-4R33M
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 33 MHz, MICROCONTROLLER, PQFP144
封装: METRIC, PLASTIC, QFP-144
文件页数: 57/84页
文件大小: 1082K
代理商: SAB-C167CS-4R33M
C167CS-4R
C167CS-L
Data Sheet
56
V2.2, 2001-08
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 11 associates the combinations of these three bits with the respective clock
generation mode.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock
fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
fOSC for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see Table 11). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
fCPU = fOSC × F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Table 11
C167CS Clock Generation Modes
CLKCFG
(RP0H.7-5)
CPU Frequency
fCPU = fOSC × F
External Clock
Input Range1)
1) The external clock input range refers to a CPU clock range of 10 … 40 MHz.
Notes
11 1
fOSC × 4
2.5 to 10 MHz
Default configuration
110
fOSC × 3
3.33 to 13.33 MHz
101
fOSC × 2
5 to 20 MHz
100
fOSC × 5
2 to 8 MHz
011
fOSC × 1
1 to 40 MHz
Direct drive2)
2) The maximum frequency depends on the duty cycle of the external clock signal.
010
fOSC × 1.5
6.66 to 26.66 MHz
001
fOSC / 2
2 to 50 MHz3)
3) In prescaler mode the full CPU clock range cannot be used.
CPU clock via prescaler
000
fOSC × 2.5
4 to 16 MHz
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