参数资料
型号: SAB-C515-L24N
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 24 MHz, MICROCONTROLLER, PQCC68
封装: PLASTIC, LCC-68
文件页数: 111/162页
文件大小: 771K
代理商: SAB-C515-L24N
Semiconductor Group
6-9
On-Chip Peripheral Components
C515
6.1.2.4
Detailed Output Driver Circuitry
In fact, the pullups mentioned before and included in figure 6-2, 6-4 and 6-5 are pullup
arrangements.
Figure 6-7 shows the detailed output driver (pullup arrangement) circuit of the the port 1 and 3 to 5
port lines. The basic circuitry of these ports is shown in figure 6-4. The pullup arrangement of these
port lines has one n-channel pulldown FET and three pullup FETs:
Figure 6-7
Driver Circuit of Ports 1, 3 to 6
– The pulldown FET n1 is of n-channel type. It is a very strong driver transistor which is capable
of sinking high currents (
I
OL); it is only activated if a "0" is programmed to the port pin. A short
circuit to
V
CC must be avoided if the transistor is turned on, since the high current might destroy
the FET. This also means that no “0“ must be programmed into the latch of a pin that is used
as input.
– The pullup FET p1 is of p-channel type. It is activated for two oscillator periods (S1P1 and
S1P2) if a 0-to-1 transition is programmed to the port pin, i.e. a "1" is programmed to the port
latch which contained a "0". The extra pullup can drive a similar current as the pulldown FET
n1. This provides a fast transition of the logic levels at the pin.
– The pullup FET p2 is of p-channel type. It is always activated when a "1" is in the port latch,
thus providing the logic high output level. This pullup FET sources a much lower current than
p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input
level.
MCS03230
=1
1
=1
V
CC
Port
Pin
SS
V
Q
Input Data
(Read Pin)
p1
p2
p3
n1
Delay = 1 State
_
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