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| 型号： | SAB-C515-L24N |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 24 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 88/162页 |
| 文件大小： | 771K |
| 代理商： | SAB-C515-L24N |
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Semiconductor Group
4-3
External Bus Interface
C515
4.1.2 Timing
The timing of the external bus interface, in particular the relationship between the control signals
ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b).
Data memory:
in a write cycle, the data byte to be written appears on port 0 just before WR is
activated and remains there until after WR is deactivated. In a read cycle, the
incoming byte is accepted at port 0 before the read strobe is deactivated.
Program memory: Signal PSEN functions as a read strobe.
4.1.3 External Program Memory Access
The external program memory is accessed under two conditions:
- whenever signal EA is active (low); or
- whenever the program counter (PC) content is greater than 1FFFH
When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an
output function and must not be used for general-purpose I/O. The content of the port 2 SFR
however is not affected. During external program memory fetches port 2 lines output the high byte
of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR
(depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri).
Since the C515-L has no internal program memory, accesses to program memory are always
external, and port 2 is at all times dedicated to output the high-order address byte. This means that
port 0 and port 2 of the C515-L can never be used as general-purpose I/O. This also applies to the
C515-1R when it operates with only an external program memory.
4.2
PSEN, Program Store Enable
The read strobe for external program memory fetches is PSEN. It is not activated for internal
program memory fetches. When the CPU is accessing external program memory, PSEN is
activated twice every instruction cycle (except during a MOVX instruction) no matter whether or not
the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is
not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD,
takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and
PSEN, takes 3 oscillator periods. The execution sequence for these two types of read cycles is
shown in figure 4-1 a) and b).
4.3
Overlapping External Data and Program Memory Spaces
In some applications it is desirable to execute a program from the same physical memory that is
used for storing data. In the C515 the external program and data memory spaces can be combined
by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low
active read strobe that can be used for the combined physical memory. Since the PSEN cycle is
faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.
相关PDF资料 |
PDF描述 |
|---|---|
| SAF-C515-RM | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| SAF-C515-LN | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| SAH-C515-LN | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| SAB-C515-LM | 8-BIT, 16 MHz, MICROCONTROLLER, PQFP80 |
| SAB-C515C-LM | 8-BIT, 10 MHz, MICROCONTROLLER, PQFP80 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SAB-C515-LM | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| SAB-C517A | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:8-bit CMOS MICROCONTROLLER |
| SAB-C517A-4R24M | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| SAB-C517A-4RM | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| SAB-C517A-L24M | 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
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