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| 型号： | SAF-TC11IB-64D96EBC |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 96 MHz, RISC MICROCONTROLLER, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 39/110页 |
| 文件大小： | 1303K |
| 代理商： | SAF-TC11IB-64D96EBC |
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TC11IB
Data Sheet
30
V2.4, 2004-06
Asynchronous Serial Interface (16X50)
The 16X50 is a universal asynchronous receiver/transmitter (UART) which is fully
prorammable.It supports word lengths from five to eight bits, an optional parity bit and
one or two stop bits.If enabled, the parity can be odd, even or forced to a defined state.
The 16X50 includes a 16-bit programmable baud rate generator and an 8-bit scratch
register, together with two 16-byte FIFOs -one for transmit and one for receive. It has six
modem control lines and supports a diagnostic loop-back mode. An interrupt can be
generated from any one of 10 sources. Figure 7 shows a global view of the functional
blocks of the Asynchronous Serial Interface (16X50).
Figure 7
General Block Diagram of the 16X50 Interface
The 16X50 Module communicates with the external world via five input and three output
lines located at Port 1.
The 16X50 provides serial asynchronous receive data synchronization, parallel-to-serial
and serial-to-parallel data conversions for both the transmitter and receiver sections.
These functions are necessary for converting the serial data stream into parallel data
that is required with digital data systems. Synchronization for the serial data stream is
accomplished by adding start and stops bits to the transmit data to form a data character
(character orientated protocol). Data integrity is insured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit errors.
The electronic circuitry to provide all these functions is fairly complex especially when
manufactured on a single integrated silicon chip. The 16X50 represents such an
integration with greatly enhanced features.
The 16X50 is an upward solution that provides 16 bytes of transmit and receive FIFO
memory, instead of 1 byte provided in the 16C450. The 16X50 is designed to work with
high speed modems and shared network environments, that require fast data processing
time. Increased performance is realized in the 16X50 by the larger transmit and receive
M C B 0493 7
Clo c k
C ontro l
Ad d re s s
D e c ode r
In te rru p t
C ontro l
f
16 x5 0
16 x 5 0
M odu le
Po rt
Co n tro l
P 1 .1 5 / 16x 5 0_R I
P 1 .1 4 / 16x 5 0_C TS
P 1 .1 3 / 16x 5 0_D TR
P 1 .1 2 / 16x 5 0_D S R
P 1 .1 1 / 16x 5 0_D C D
P 1 .1 0 / 16x 5 0_R TS
P 1 .9 / 1 6 x 5 0 _ T x D
P 1 .8 / 1 6 x 5 0 _ R x D
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