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| 型号： | SAF-TC11IB-64D96EBC |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 96 MHz, RISC MICROCONTROLLER, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 65/110页 |
| 文件大小： | 1303K |
| 代理商： | SAF-TC11IB-64D96EBC |
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TC11IB
Data Sheet
54
V2.4, 2004-06
System Timer
The STM within the TC11IB is designed for global system timing applications requiring
both high precision and long range. The STM provides the following features:
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Driven by clock,
fSTM (identical with the system clock fSYS = 48MHz).
Counting begins at power-on reset
Continuous operation is not affected by any reset condition except power-on reset
The STM is an upward counter, running with the system clock frequency. It is enabled
per default after reset, and immediately starts counting up. Other than via reset, it is no
possible to affect the contents of the timer during normal operation of the application, it
can only be read, but not written to. Depending on the implementation of the clock control
of the STM, the timer can optionally be disabled or suspended for power-saving and
debugging purposes via a clock control register.
The maximum clock period is 256
× f
STM. At fSTM = 48 MHz, for example, the STM
counts 47.6 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflow.
Figure 14
Block Diagram of the STM Module
STM M odule
00
H
CA P
TIM 6
TIM 5
TIM 4
TIM 3
TIM 2
TIM 1
TIM 0
00
H
55
47
39
31
23
15
7
56 -B it S y s tem Tim e r
A ddres s
De c o d e r
Clo c k
Co n tro l
E n able /
Dis a b le
PO R S T
f
STM
M C A 04795
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