参数资料
型号: SAX-XC878M-16FFI5V
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 24 MHz, RISC MICROCONTROLLER, PQFP64
封装: PLASTIC, TQFP-64
文件页数: 121/141页
文件大小: 2385K
代理商: SAX-XC878M-16FFI5V
XC878CLM
Functional Description
Data Sheet
73
V1.1, 2009-08
Figure 19
CGU Block Diagram
Direct Drive (PLL Bypass Operation)
During PLL bypass operation, the system clock has the same frequency as the external
clock source.
(3.1)
PLL Mode
The CPU clock is derived from the oscillator clock, divided by the NR factor (PDIV),
multiplied by the NF factor (NDIV), and divided by the OD factor (KDIV). PLL output must
PLL
PLL
core
lock
detect
NF:1
NR:1
fvco
fn
fp
OSC
fosc
OD:1
fSYS
NDIV
PLL_LOCK
PLLBYP
KDIV
PDIV
Wrapper
PLL
watchdog
External
oscillator
watchdog
PLLPD
EXTOSCR
OSCSS
PLLR
Switching
circuitry
OSC
SYS
f
=
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