参数资料
型号: SC16C2550BIBS,151
厂商: NXP Semiconductors
文件页数: 2/31页
文件大小: 0K
描述: IC UART DUAL W/FIFO 32-HVQFN
产品培训模块: Stand-Alone UARTs
标准包装: 490
特点: 故障启动位检测
通道数: 2,DUART
FIFO's: 16 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-HVQFN(5x5)
包装: 托盘
产品目录页面: 828 (CN2011-ZH PDF)
其它名称: 568-3259
935280309151
SC16C2550BIBS-S
SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
10 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.2 Internal registers
The SC16C2550B provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 5. The UART registers function as data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control
Register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM) and a
user-accessible Scratchpad Register (SPR).
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
Table 4.
Serial port selection
Chip Select
Function
CSA, CSB = 1
none
CSA = 0
UART channel A
CSB = 0
UART channel B
Table 5.
Internal registers decoding
A2
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1]
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
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