参数资料
型号: SC16C2550BIBS,151
厂商: NXP Semiconductors
文件页数: 28/31页
文件大小: 0K
描述: IC UART DUAL W/FIFO 32-HVQFN
产品培训模块: Stand-Alone UARTs
标准包装: 490
特点: 故障启动位检测
通道数: 2,DUART
FIFO's: 16 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-HVQFN(5x5)
包装: 托盘
产品目录页面: 828 (CN2011-ZH PDF)
其它名称: 568-3259
935280309151
SC16C2550BIBS-S
SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
6 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
5.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
HVQFN32 DIP40 PLCC44 LQFP48
A0
19
28
31
28
I
Address 0 select bit. Internal register address selection.
A1
18
27
30
27
I
Address 1 select bit. Internal register address selection.
A2
17
26
29
26
I
Address 2 select bit. Internal register address selection.
CSA
8
14
16
10
I
Chip Select A, B (active LOW). This function is associated
with individual channels, A through B. These pins enable data
transfers between the user CPU and the SC16C2550B for the
channel(s) addressed. Individual UART sections (A, B) are
addressed by providing a logic 0 on the respective CSA, CSB
pin.
CSB
9
15
17
11
I
D0
27
1
2
44
I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data
bus for transferring information to or from the controlling CPU.
D0 is the least signicant bit and the rst data bit in a transmit
or receive serial data stream.
D1
28
2
3
45
I/O
D2
29
3
4
46
I/O
D3
30
4
5
47
I/O
D4
31
5
6
48
I/O
D5
32
6
7
1
I/O
D6
1
7
8
2
I/O
D7
2
8
9
3
I/O
GND
13
20
22
17
I
Signal and power ground.
INTA
21
30
33
30
O
Interrupt A, B (3-state). This function is associated with
individual channel interrupts, INTA, INTB. INTA, INTB are
enabled when MCR bit 3 is set to a logic 1, interrupts are
enabled in the Interrupt Enable Register (IER) and is active
when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer
empty or when a modem status ag is detected.
INTB
20
29
32
29
O
IOR
14
21
24
19
I
Read strobe (active LOW strobe). A logic 0 transition on this
pin will load the contents of an internal register dened by
address bits A0 to A2 onto the SC16C2550B data bus
(D0 to D7) for access by external CPU.
IOW12
18
20
15
I
Write strobe (active LOW strobe). A logic 0 transition on this
pin will transfer the contents of the data bus (D0 to D7) from the
external CPU to an internal register that is dened by address
bits A0 to A2.
OP2A
22
31
35
32
O
Output 2 (user-dened). This function is associated with
individual channels, A through B. The state at these pin(s) are
dened by the user and through MCR register bit 3. INTA, INTB
are set to the active mode and OP2 to logic 0 when MCR[3] is
set to a logic 1. INTA, INTB are set to the 3-state mode and
OP2 to a logic 1 when MCR[3] is set to a logic 0. See Table 18
Since these bits control both the INTA, INTB operation and
OP2 outputs, only one function should be used at one time, INT
or OP2.
OP2B
7
13
15
9
O
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