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| 型号： | SC16C2550IB48,157 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 18/46页 |
| 文件大小： | 0K |
| 描述： | IC DUART SOT313-2 |
| 标准包装： | 1,250 |
| 特点： | 2 通道 |
| 通道数： | 2，DUART |
| FIFO's： | 16 字节 |
| 电源电压： | 2.5V，3.3V，5V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 管件 |
| 其它名称： | 935270020157 SC16C2550IB48 SC16C2550IB48-ND |
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Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
25 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C2550 and
the CPU.
Table 18:
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break
indication is in the current FIFO data. This bit is cleared when
there are no remaining error ags associated with the remaining
data in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This
bit is set to a logic 1 whenever the transmit holding register and the
transmit shift register are both empty. It is reset to logic 0 whenever
either the THR or TSR contains a data character. In the FIFO
mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit
shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty
indicator. This bit indicates that the UART is ready to accept a new
character for transmission. In addition, this bit causes the UART to
issue an interrupt to CPU when the THR interrupt enable is set.
The THR bit is set to a logic 1 when a character is transferred from
the transmit holding register into the transmitter shift register. The
bit is reset to a logic 0 concurrently with the loading of the
transmitter holding register by the CPU. In the FIFO mode, this bit
is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0
for one character frame time). In the FIFO mode, only one break
character is loaded into the FIFO.
3
LSR[3]
Framing error.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a
valid stop bit(s). In the FIFO mode, this error is associated with
the character at the top of the FIFO.
2
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition.
Logic 1 = Parity error. The receive character does not have
correct parity information and is suspect. In the FIFO mode, this
error is associated with the character at the top of the FIFO.
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| SC16C2550IA44,518 | IC DUART SOT187-2 |
| SC16C2550IA44,512 | IC DUART SOT187-2 |
| VI-B7N-IX-F1 | CONVERTER MOD DC/DC 18.5V 75W |
| SC16C2550BIN40,112 | IC UART DUAL W/FIFO 40-DIP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C2550IN40 | 制造商:PHILIP 功能描述: |
| SC16C2550IN40,112 | 功能描述:IC UART DUAL W/FIFO 40-DIP RoHS:是 类别:集成电路 (IC) >> 接口 - UART（通用异步接收器/发送器） 系列:- 标准包装:250 系列:- 特点:* 通道数:2，DUART FIFO's:16 字节 规程:RS232，RS485 电源电压:2.25 V ~ 5.5 V 带并行端口:- 带自动流量控制功能:是 带IrDA 编码器/解码器:是 带故障启动位检测功能:是 带调制解调器控制功能:是 带CMOS:是 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:托盘 其它名称:XR16L2551IM-F-ND |
| SC16C2552 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
| SC16C2552B | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs |
| SC16C2552BIA44 | 功能描述:UART 接口集成电路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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