参数资料
型号: SC16C550BIB48,128
厂商: NXP Semiconductors
文件页数: 10/48页
文件大小: 0K
描述: IC UART SINGLE W/FIFO 48-LQFP
标准包装: 2,000
特点: 可编程
通道数: 1,UART
FIFO's: 16 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
其它名称: 935274388128
SC16C550BIB48-F
SC16C550BIB48-F-ND
SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
18 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.
Register descriptions
Table 9 details the assigned bit functions for the twelve SC16C550B internal registers.
The assigned bit functions are more fully dened in Section 7.1 through Section 7.10.
[1]
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
[2]
These registers are accessible only when LCR[7] is set to a logic 0.
[3]
These functions are not supported in the HVQFN32 package, and should not be written.
[4]
OUT2 pin is not supported in the HVQFN32 package.
[5]
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Table 9.
SC16C550B internal registers
A2
A1
A0
Register
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
General Register Set[2]
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
IER
00
modem
status
interrupt
receive
line status
interrupt
transmit
holding
register
receive
holding
register
0
1
0
FCR
00
RX
trigger
(MSB)
RX
trigger
(LSB)
reserved reserved
DMA
mode
select[3]
TX FIFO
reset
RX FIFO
reset
FIFO
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
0
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
LCR
00
divisor
latch
enable
set break set parity even
parity
enable
stop bits
word
length
bit 1
word
length
bit 0
1
0
MCR
00
reserved
auto ow
control
enable
loopback
OUT2[4]
RTS
DTR
1
0
1
LSR
60
FIFO
data
error
transmit
empty
transmit
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
0
MSR
X0
DCD
RI
DSR
CTS
DCD
RI
DSR
CTS
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Special Register Set[5]
0
DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
DLM
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
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