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| 型号： | SC16C554IB64,128 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 21/55页 |
| 文件大小： | 0K |
| 描述： | IC UART QUAD SOT314-2 |
| 标准包装： | 1,500 |
| 通道数： | 4，QUART |
| FIFO's： | 16 字节 |
| 电源电压： | 2.5V，3.3V，5V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
| 其它名称： | 935270074128 SC16C554IB64-T SC16C554IB64-T-ND |
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Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 05 — 10 May 2004
28 of 55
9397 750 13132
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 14:
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch and enhanced feature register enabled.
6
LCR[6]
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
5
LCR[5]
Set parity. If the parity bit is enabled, LCR[5] selects the forced
parity format. Programs the parity conditions (see Table 15).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a
logical 1 for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a
logical 0 for the transmit and receive data.
4
LCR[4]
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be
programmed to check the same format (normal default
condition).
Logic 1 = EVEN Parity is generated by forcing an even number
of logic 1s in the transmitted data. The receiver must be
programmed to check the same format.
3
LCR[3]
Parity enable. Parity or no parity can be selected via this bit.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during the transmission,
receiver checks the data and parity for transmission errors.
2
LCR[2]
Stop bits. The length of stop bit is specied by this bit in
conjunction with the programmed word length (see Table 16).
Logic 0 or cleared = default condition.
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 17).
Logic 0 or cleared = default condition.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C554IB80 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C554IB80,528 | 功能描述:UART 接口集成电路 Quad UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C554IB80,551 | 功能描述:UART 接口集成电路 16C 2.5V-5V 4CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C554IB80,557 | 功能描述:UART 接口集成电路 16C 2.5V-5V 4CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C650A | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 32-byte FIFO and infrared (IrDA) encoder/decoder |
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