参数资料
型号: SC16IS762IBS,151
厂商: NXP Semiconductors
文件页数: 5/60页
文件大小: 0K
描述: IC UART DUAL I2C/SPI 32-HVQFN
产品培训模块: Bridge Solutions
Stand-Alone UARTs
I²C Bus Fundamentals
特色产品: NXP - I2C Interface
标准包装: 490
特点: 低电流
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS485
电源电压: 2.5V, 3.3V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-HVQFN(5x5)
包装: 托盘
产品目录页面: 828 (CN2011-ZH PDF)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名称: 568-2240
935279293151
SC16IS762IBS-S
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
13 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.4 Hardware Reset, Power-On Reset (POR) and Software Reset
These three reset methods are identical and will reset the internal registers as indicated in
Table 4 summarizes the state of register after reset.
Remark: Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the
top-level reset signal RESET, POR and Software Reset, that is, they hold their
initialization values during reset.
Table 5 summarizes the state of output signals after reset.
Table 4.
Register reset
Register
Reset state
Interrupt Enable Register
all bits cleared
Interrupt Identification Register
bit 0 is set; all other bits cleared
FIFO Control Register
all bits cleared
Line Control Register
reset to 0001 1101 (0x1D)
Modem Control Register
all bits cleared
Line Status Register
bit 5 and bit 6 set; all other bits cleared
Modem Status Register
bits 3:0 cleared; bits 7:4 input signals
Enhanced Features Register
all bits cleared
Receive Holding Register
pointer logic cleared
Transmit Holding Register
pointer logic cleared
Transmission Control Register
all bits cleared
Trigger Level Register
all bits cleared
Transmit FIFO level
reset to 0100 0000 (0x40)
Receive FIFO level
all bits cleared
I/O direction
all bits cleared
I/O interrupt enable
all bits cleared
I/O control
all bits cleared
Extra Features Control Register
all bits cleared
Table 5.
Output signals after reset
Signal
Reset state
TX
HIGH
RTS
HIGH
I/Os
inputs
IRQ
HIGH by external pull-up
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