参数资料
型号: SC186ULTRT
厂商: Semtech
文件页数: 13/18页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 16MLPQ
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 3.3 V
输入电压: 2.9 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 1.5MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-UFQFN 裸露焊盘
包装: 标准包装
供应商设备封装: 16-MLPQ-UT(3x3)
其它名称: SC186ULDKR
SC186
Applications Information
Detailed Description
The SC186 is a synchronous step-down PWM (Pulse Width
Modulated) DC-DC converter utilizing a 1.5MHz fixed-fre-
quency voltage mode architecture. The device is designed
to operate in fixed-frequency PWM mode and will enter
PSAVE (power save) mode at light loads to maximize effi-
ciency. The switching frequency is chosen to minimize the
size of the external inductor and capacitors while main-
If the output load current increases enough to cause V OUT
to decrease below the PSAVE exit threshold (V OUT - 4%),
the device automatically exits PSAVE and operates in con-
tinuous PWM mode. Note that the PSAVE high and low
threshold levels are both set at or above V OUT to minimize
undershoot when the SC186 exits PSAVE. Figure 1 illus-
trates the transitions from PWM mode to PSAVE mode and
back to PWM mode.
taining high efficiency.
Operation
During normal operation, the PMOS MOSFET is activated
on each rising edge of the internal oscillator. The period is
set by the onboard oscillator when in PWM mode. The
device has an internal synchronous NMOS rectifier and
does not require a Schottky diode on the LX pin. The
Load
Demand
( I OUT )
V OUT +2%
V OUT
OFF
V LX
device operates as a buck converter in PWM mode with a
fixed frequency of 1.5MHz at medium to high loads. At
light loads the part will enter PSAVE mode to maximize
efficiency.
Power Save Mode Operation
When the load current decreases below the PSAVE thresh-
old, PWM switching stops and the device automatically
enters PSAVE mode. This threshold varies depending upon
the input voltage and output voltage setting, optimizing
efficiency for all possible load currents. While in PSAVE
mode, output voltage regulation is controlled by a series of
bursts in switching. During a burst, the inductor current is
limited to a peak value which controls the on-time of the
PMOS switch. After reaching this peak, the PMOS switch is
disabled and the inductor current is forced to near 0mA.
Switching bursts continue until the output voltage climbs
to V OUT +2% or until the PSAVE current limit is reached.
Switching is then stopped to eliminate switching losses,
enhancing overall efficiency. Switching resumes when the
output voltage reaches the lower threshold of V OUT and
continues until the upper threshold again is reached. Note
that the output voltage is regulated hysteretically while in
PSAVE mode between V OUT and V OUT + 2%. The period and
duty cycle while in PSAVE mode are solely determined by
V IN and V OUT until PWM mode resumes. This can result in the
switching frequency being much lower than the PWM
mode frequency.
BURST
V OUT -4%
PSAVE
EXIT
PWM Mode at PSAVE Mode at PWM Mode at
Medium / High Light Load Medium / High
Load Load
Time
Figure 1 — Transitions between PWM and PSAVE Modes
Protection Features
The SC186 provides the following protection features:
? Current Limit
? Over-Voltage Protection
? Soft-Start Operation
? Thermal Shutdown
Current Limit & OCP
The internal PMOS power device in the switching stage is
protected by a current limit feature. If the inductor current
is above the PMOS current limit for 16 consecutive cycles,
the part enters foldback current limit mode and the output
current is limited to the current limit holding current
(I CL_HOLD ) which is approximately 1A. Under this condition,
the output voltage will be the product of I CL_HOLD and the
13
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