参数资料
型号: SC2440TETRT
厂商: Semtech
文件页数: 11/26页
文件大小: 0K
描述: IC REG BUCK 2A DL 16TSSOP
标准包装: 1
类型: 降压(降压)
输出数: 2
输入电压: 2.8 V ~ 20 V
PWM 型: 电流模式
频率 - 开关: 1.4MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 标准包装
供应商设备封装: 16-TSSOP
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC2440TEDKR
SC2440
POWER MANAGEMENT
Applications Information
D 1 =
= 0 . 71
D 2 =
= 0 . 93 .
1 ? D 1
1 ? D 2
= 1 . 73 MHz to ensure locking.
output voltage will not be able to reach its set value in
continuous-conduction mode.
Example : Determine the maximum operating frequency
of a dual 3.3V to 1.8V and 3.3V to 2.5V switching
regulator using the SC2440.
Assuming that V D = 0.45V, V CESAT = 0.25V and V IN = 2.97V
(10% low line), the duty ratios D 1 and D 2 of the 1.8V
and 2.5V converters can be calculated using (2).
1 . 8 + 0 . 45
2 . 97 + 0 . 45 ? 0 . 25
2 . 5 + 0 . 45
2 . 97 + 0 . 45 ? 0 . 25
The maximum operating frequencies of the 1.8V and the
2.5V converters are therefore = 2 . 4 MHz and
120 ns
= 580 KHz respectively..
120 ns
the set frequency of master oscillator because the
amplitudes of the internal sawtooth ramp and slope
compensation ramp will both be significantly reduced.
Example: Choose the value of R OSC to externally
synchronize the SC2440 to 2MHz per channel .
The required synchronizing clock frequency = 2 times
the channel frequency = 4MHz.
For a given R OSC , the free-running channel frequency
has a tolerance of ±15%.
Set the nominal free-running channel frequency to
2 MHz
1 . 15
Looking up the graph “Channel Frequency vs. R OSC ” in
the Typical Characteristics, R OSC = 9.31K ? for a set
frequency of 1.73MHz.
With ±15% tolerance, the set channel frequency can vary
from 0 . 85 ? ( 1 . 73 ) = 1 . 47 MHz to 1 . 15 ? ( 1 . 73 ) = 2 MHz .
Therefore
Transient headroom requires that channel frequency be
lower than 580KHz.
Synchroniz ing Frequency
Lowest Free ? running Frequency
=
2
1 . 47
= 1 . 36 .
? I L =
( V OUT + V D )( 1 ? D ) ( V OUT + V D )( V IN ? V OUT ? V CESAT )
( V IN + V D ? V CESAT ) fL
External Synchronization
The SYNC input buffer is positive-edge triggered and TTL-
compatible ( V IL < 0 . 8 V and V IH > 2 V ). The free-running
master oscillator generates a periodic sawtooth ramp
between two threshold voltages. A faster external clock
applied to the SYNC pin discharges the internal ramp
before it reaches its upper threshold, thus locking the
internal oscillator. As shown in Figure 2, the master
oscillator is being synchronized not the individual phases
(see Figure 2). The synchronizing frequency should be
twice the desired channel frequency. Bench test shows
that an external clock with frequency ranging from slightly
below twice to at least 3.5 times the channel free-
running frequency is capable of locking the master
oscillator. To ensure frequency locking, the external clock
frequency should be at least twice the highest free-
running channel frequency. The frequency of the
synchronizing clock should not be higher than 1.6 times
Inductor Selection
The inductor ripple current ? I L for a non-synchronous
step-down converter in continuous-conduction mode is
=
fL
(3)
where f is the switching frequency and L is the
inductance.
In current-mode control, the slope of the modulating
(sensed switch current) ramp should be steep enough
to lessen jittery tendency but not so steep that large
flux swing decreases efficiency. Inductor ripple current
? I L between 25-40% of the peak inductor current limit is
a good compromise. Inductors so chosen are optimized
? 2005 Semtech Corp.
11
www.semtech.com
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