参数资料
型号: SC2440TETRT
厂商: Semtech
文件页数: 17/26页
文件大小: 0K
描述: IC REG BUCK 2A DL 16TSSOP
标准包装: 1
类型: 降压(降压)
输出数: 2
输入电压: 2.8 V ~ 20 V
PWM 型: 电流模式
频率 - 开关: 1.4MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 标准包装
供应商设备封装: 16-TSSOP
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC2440TEDKR
SC2440
POWER MANAGEMENT
Applications Information
Overload / Short-Circuit Protection
Each current limit comparator in the SC2440 limits the
peak inductor current to 2.6A. The regulator output
voltage will fall if the load is increased above the current
limit. If overload is detected (the output voltage falls
below 74% of the set voltage), then the regulator will be
shut off. An internal 0.8μA current sink starts to
discharge the soft-start capacitor. As the soft-start
capacitor is discharged below 1V, the discharge current
source turns off and the soft-start capacitor is recharged
with a 1.8μA current source. The regulator undergoes
soft-start. During soft-start (1V < V SS < 2V), the overload
shutdown latch in Figure 3 cannot be set. When V SS
exceeds 2V, the set input of the overload latch is no
longer blanked. If V FB is still below 0.74V, then the
regulator will undergo shutdown and restart. The soft-
start process should allow the output voltage to reach
74% of its final value before C SS is charged above 2V.
Figures 10(a) and 10(b) show the timing diagrams of
successful and failed start-up waveforms respectively.
The soft-start interval should also be made sufficiently
long so that the output voltage rises monotonically and
it does not overshoot its final voltage by more than 5%.
When starting into a shorted output, the SC2440 will
repeatedly start and shut off (“hiccup”). V SS and V COMP
will appear as asymmetrical triangular waves [Figure
10(b)].
Power Good Indicators
The PGOOD pins (Pins 11 and 14) are the open-collector
outputs of the power good comparators. These slow
comparators are incorporated with small amount of
hysteresis. The FB low-to-high trip voltage of the power
good comparators is 90% of the final regulation voltage.
A pull-up resistor from each PGOOD pin to the input supply
or the regulator output set the logic high level of the
comparator.
The power good comparator output becomes valid
provided that V IN is above 0.9V. In shutdown the power
good output is actively pulled low. A power good pull-up
resistor tied to the input will therefore increase current
drain during shutdown. Tying the power good pull-up
resistor to the regulator output is preferred, as this will
minimize the shutdown supply current. In shutdown there
SS1
PGOOD1
SS1
CONTROL1
CSS1
SC2440
OFF ON
CSS1
SC2440
PGOOD1
SS2
PGOOD2
SS2
PGOOD2
CONTROL2
CONTROL1
CONTROL2
CSS2
OFF
OFF
ON
T D
ON
(a)
CSS2
(b)
Figure 11. Sequencing the Outputs by (a) Delaying Release of one Channel Relative to
the Other and (b) Using the PGOOD of one Channel to Control the Other.
? 2005 Semtech Corp.
17
www.semtech.com
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