参数资料
型号: SC2440TETRT
厂商: Semtech
文件页数: 18/26页
文件大小: 0K
描述: IC REG BUCK 2A DL 16TSSOP
标准包装: 1
类型: 降压(降压)
输出数: 2
输入电压: 2.8 V ~ 20 V
PWM 型: 电流模式
频率 - 开关: 1.4MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 标准包装
供应商设备封装: 16-TSSOP
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC2440TEDKR
SC2440
POWER MANAGEMENT
Applications Information
v OUT
v COMP
ω p 2 ≈ ?
nI OUT n
= ?
V OUT C 1
R OUT C 1
is no voltage at the switching regulator output or current
in the PGOOD pull-up resistor. If the PGOOD output high
level (= V OUT ) is unacceptably low, then power good pull-
up from the input or a separate power supply will be the
only choice.
Sequencing the Outputs
As mentioned above, pulling either soft-start pin low with
an external transistor shuts off the corresponding
regulator (Figure 11). Releasing the soft-start pin enables
that channel and allows it to start. Delaying the release
of the soft-start pin of one channel with respect to the
other is a straightforward way of sequencing the outputs.
Figure 11(a) shows this method using two external
transistors M 1 and M 2 . M 1 is turned off first, allowing
channel 1 to start. Channel 2 is then enabled after time
T D .
The PGOOD output of one channel can also be used in
conjunction with the soft-start pin of the other channel
to delay start of that regulator. This method is depicted
in Figure 11(b). SS2 is pulled low and channel 2 is kept
off until channel 1 output rises to 90% of its set voltage.
A drawback of this approach is that only PGOOD2 is
available as a logic output.
Loop Compensation
Figure 12 shows a simplified equivalent circuit of a step-
down converter. The power stage, which consists of the
current-mode PWM comparator, the power switch, the
freewheeling diode and the inductor, feeds the output
network. The power stage can be modeled as a voltage-
controlled current source, producing an output current
proportional to its controlling input V COMP . Its
transconductance G MP is 5.7 ? -1 . With the current loop
closed, the control-to-output transfer function has
a dominant-pole p 2 located at a frequency slightly higher
than that of the output filter pole.
(8)
where C 1 is the output capacitor, R OUT is the equivalent
load resistance and n (depending on duty ratio, slope
compensation, frequency and passive components) is
usually between 1 and 2.
If C 1 is ceramic, then its ESR zero can be neglected as it
situates well beyond half the switching frequency. The
low frequency gain of the control-to-output transfer
function is simply the product of power stage
transconductance and the equivalent load resistance
(Figure 13).
The transfer functions of the feedback network and the
error amplifier are:
GMP = 5.7 ?
V
IN
POWER
STAGE
-1
C11
R1
I OUT
ESR
V OUT
R OUT
C1
GMA = -1 -
V COMP
280 μ?
+
FB
C6
R5
RO
1V
R2
C5
VOLTAGE
REFERENCE
Figure 12. Simplified Control Loop Equivalent Circuit
? 2005 Semtech Corp.
18
www.semtech.com
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