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参数资料
| 型号： | SC26C92A1N-S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封装： | 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40 |
| 文件页数： | 13/31页 |
| 文件大小： | 221K |
| 代理商： | SC26C92A1N-S |
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Philips Semiconductors
Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31
20
SRA[6] – Channel A Framing Error
This bit, when set, indicates that a stop bit was not detected (not a
logical 1) when the corresponding data character in the FIFO was
received. The stop bit check is made in the middle of the first stop
bit position.
SRA[5] – Channel A Parity Error
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity.
In the special multidrop mode the parity error bit stores the receive
A/D (Address/Data) bit.
SRA[4] – Channel A Overrun Error
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost.
This bit is cleared by a ‘reset error status’ command.
SRA[3] – Channel A Transmitter Empty (TxEMTA)
This bit will be set when the transmitter underruns, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when
the transmitter is first enabled and at any time it is re-enabled after
either (a) reset, or (b) the transmitter has assumed the disabled
state. It is always set after transmission of the last stop bit of a
character if no character is in the THR awaiting transmission.
It is reset when the THR is loaded by the CPU, a pending
transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the underrun condition.
SRA[2] – Channel A Transmitter Ready (TxRDYA)
This bit, when set, indicates that the transmit FIFO is not full and
ready to be loaded with another character. This bit is cleared when
the transmit FIFO is loaded by the CPU and there are (after this
load) no more empty locations in the FIFO. It is set when a
character is transferred to the transmit shift register. TxRDYA is
reset when the transmitter is disabled and is set when the
transmitter is first enabled. Characters loaded to the TxFIFO while
this bit is 0 will be lost. This bit has different meaning from ISR[0].
SRA[1] – Channel A FIFO Full (FFULLA)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all eight FIFO positions are occupied. It is reset
when the CPU reads the receive FIFO. If a character is waiting in
the receive shift register because the FIFO is full, FFULLA will not
be reset when the CPU reads the receive FIFO. This bit has
different meaning from ISR1 when MR1 6 is programmed to a ‘1’.
SRA[0] – Channel A Receiver Ready (RxRDYA)
This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the FIFO and reset
when the CPU reads the receive FIFO, only if (after this read) there
are no more characters in the FIFO. The RxFIFO becomes empty.
SRB – Channel B Status Register
The bit definitions for this register are identical to the bit definitions
for SRA, except that all status applies to the Channel B receiver and
transmitter and the corresponding inputs and outputs.
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
0
The complement of OPR[7].
1
The Channel B transmitter interrupt output which is the comple-
ment of ISR[4]. When in this mode OP7 acts as an open- drain
output. Note that this output is not masked by the contents of the
IMR.
OPCR[6] – OP6 Output Select
This bit programs the OP6 output to provide one of the following:
0
The complement of OPR[6].
1
The Channel A transmitter interrupt output which is the comple-
ment of ISR[0]. When in this mode OP6 acts as an open- drain
output. Note that this output is not masked by the contents of the
IMR.
OPCR[5] – OP5 Output Select
This bit programs the OP5 output to provide one of the following:
0
The complement of OPR[5].
1
The Channel B receiver interrupt output which is the complement
of ISR[5]. When in this mode OP5 acts as an open-drain output.
Note that this output is not masked by the contents of the IMR.
OPCR[4] – OP4 Output Select
This field programs the OP4 output to provide one of the following:
0
The complement of OPR[4].
1
The Channel A receiver interrupt output which is the complement
of ISR[1]. When in this mode OP4 acts as an open-drain output.
Note that this output is not masked by the contents of the IMR.
OPCR[3:2] – OP3 Output Select
This bit programs the OP3 output to provide one of the following:
00 The complement of OPR[3].
01 The counter/timer output, in which case OP3 acts as an open-
drain output. In the timer mode, this output is a square wave at
the programmed frequency. In the counter mode, the output
remains High until terminal count is reached, at which time it
goes Low. The output returns to the High state when the counter
is stopped by a stop counter command. Note that this output is
not masked by the contents of the IMR.
10 The 1X clock for the Channel B transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted, a
free running 1X clock is output.
11 The 1X clock for the Channel B receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1X clock is output.
OPCR[1:0] – OP2 Output Select
This field programs the OP2 output to provide one of the following:
00 The complement of OPR[2].
01 The 16X clock for the Channel A transmitter. This is the clock
selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] =
1111.
10 The 1X clock for the Channel A transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted, a
free running 1X clock is output.
11 The 1X clock for the Channel A receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1X clock is output.
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| SC26C92C1A | 功能描述:UART 接口集成电路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC26C92C1A,512 | 功能描述:UART 接口集成电路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC26C92C1A,518 | 功能描述:UART 接口集成电路 5V 2 CH UART COM TEMP RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC26C92C1A,529 | 功能描述:UART 接口集成电路 5V 2CH UART COM TEMP RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC26C92C1A | 制造商:NXP Semiconductors 功能描述:CMOS DUAL UART SMD 26C92 PLCC44 |
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