参数资料
型号: SC286ULTRT
厂商: Semtech
文件页数: 15/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 28MLPQ
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 3.3 V
输入电压: 2.9 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 1.6MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-UFQFN 裸露焊盘
包装: 标准包装
供应商设备封装: 28-MLPQ(4x4)
其它名称: SC286ULDKR
SC286
Applications Information (continued)
To guarantee an operating junction temperature of less
than 125°C, Figure 3 shows the maximum allowable total
power loss versus temperature. The curve is based upon
the junction temperature of either channel reaching a
maximum of 125°C. Each channel of SC286 can support
up to 4A load current. Figure 4 shows the maximum
allowable power loss in channel B versus power loss in
channel A for a range of temperatures.
4.5
Shut Down
When all CTL pins for a channel are low, the device will run
in shutdown mode, drawing less than 1μA from the input
power supply. The internal switches and band-gap voltage
will be immediately turned off.
Thermal Shutdown
The device has an independent thermal shutdown feature
for each channel to protect the SC286 if the junction tem-
perature exceeds 160°C. During thermal shutdown, the
on-chip power devices are disabled, floating the LX
4
V IN = 5V; V OUT = 1.2V
output. When the temperature drops by 10°C, it will initi-
ate a soft start cycle to resume normal operation.
3.5
3
2.5
V IN = 3.3V; V OUT = 1.2 V
V IN = 5V; V OUT = 3.3V
Under-Voltage Lockout
Under-Voltage Lockout (UVLO) is enabled when the input
voltage for each channel drops below the UVLO threshold.
This prevents the device from entering an ambiguous
state in which regulation cannot be maintained. Hysteresis
of approximately 300mV is included to prevent chattering
2
25
35
45
55 65 75
Ambient Temperature (°C)
85
95
105
near the threshold. When the AVIN voltage rises back to
the turn-on threshold and CTL X is high, the soft-start mode
is initiated.
Figure 3 — Maximum allowable total loss versus
temperature for a maximum junction temperature of
125°C
Power Good
The power good (PGOOD) for each channel is an open-
drain output. When the output voltage for each channel
drops below 10% of the nominal voltage, the PGOOD pin
1.8
1.6
1.4
1.2
1
0.8
T A = 25° C
T A = 70° C
T A = 85° C
T A = 55° C
for that channel is pulled low after a 20μs delay. During
start-up, PGOOD will be asserted 1.8ms (typ.) after the
output voltage reaches 90% of the final regulation voltage.
The faults of over voltage, fold-back current limit mode
and thermal shutdown will force PGOOD low after a 20 μ s
delay. When recovering from a fault, PGOOD will be
asserted 2ms (typ.) after Vout reaches 90% of the final
regulation voltage.
0.6
0.4
0.2
0
0
0.2
0.4
0.6 0.8 1 1.2
Power Loss of Channel A (W)
1.4
1.6
1.8
Figure 4 — Maximum allowable power loss in channel
B versus power loss in channel A for a range of
temperatures (both channels same current)
15
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