参数资料
| 型号： | SC286ULTRT |
| 厂商： | Semtech |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 28MLPQ |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 3.3 V |
| 输入电压： | 2.9 V ~ 5.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 1.6MHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-UFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 28-MLPQ（4x4） |
| 其它名称： | SC286ULDKR |
SC286
Applications Information (continued)
PCB Layout Considerations
The layout diagram in Figure 5 shows a recommended
top-layer PCB for the SC286 and supporting components.
Figure 6 shows the bottom layer for this PCB. Fundamental
layout rules must be followed since the layout is critical for
achieving the performance specified in the Electrical
Characteristics table. Poor layout can degrade the perfor-
mance of the DC-DC converter and can contribute to EMI
problems, ground bounce, and resistive voltage losses.
Poor regulation and instability can result.
The following guidelines are recommended when devel-
oping a PCB layout:
1. The input capacitor, C IN (for applicable channel) should
be placed within 1mm of the PVIN and PGND pins.
This capacitor provides a low impedance loop for the
pulsed currents present at the buck converter’s input.
Use short wide traces to connect as closely to the IC
as possible. This will minimize EMI and input voltage
ripple by localizing the high frequency current pulses.
2. Keep the LX pin traces as short as possible to minimize
pickup of high frequency switching edges to other
parts of the circuit. C OUT and L (for applicable channel)
should be connected as close as possible between the
LX and PGND pins, with a direct return to the PGND
pin from C OUT . The gap between the LX trace and the
other traces should be at least 0.25mm (10 mils).
3. Route the output voltage feedback/sense path away
from the inductor and LX node to minimize noise and
magnetic interference.
4. Use a ground plane referenced to the SC286 PGND
pin. Use several vias to connect to the component
side ground to further reduce noise and interference
on sensitive circuit nodes.
5. If possible, minimize the resistance from the VOUT and
PGND pins to the load (for applicable channel). This
will reduce the voltage drop on the ground plane and
improve the load regulation. And it will also improve
the overall efficiency by reducing the copper losses
Figure 5 — Recommended PCB Layout (Top Layer)
Figure 6 — Recommended PCB Layout (Bottom Layer)
on the output and ground planes.
6. The filter capacitor, C AVIN , should be placed as close
to the AVIN and AGND pins as possible. This reduces
noise coupling into the internal circuit.
17
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