参数资料
| 型号： | SC412AMLTRT |
| 厂商： | Semtech |
| 文件页数： | 10/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-MLP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 325kHz |
| 占空比： | 90% |
| 电源电压： | 3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-MLP |
| 包装： | 标准包装 |
| 其它名称： | SC412AMLDKR |
NOT RECOMMENDED FOR NEW DESIGN
POWER MANAGEMENT
Applications Information (continued)
SC412A
The RDS ON sensing circuit is shown in Figure 4 with R ILIM =
R1 and RDS ON of Q2 .
The following over-current equation can be used for both
RDS ON or resistive sensing. For RDS ON sensing, the MOSFET
RDS ON rating is used for the value of R SENSE .
+5V
D1
VBAT
Q1
+
C1
R ILIM
IL OC (Valley) = 10 μ A ? ———
R SENSE
BST
DH
LX
ILIM
VDD
DL
GND
SC412A
C2
R1
Q2
D2
L
+
C3
VOUT
Power Good Output
The power good (PGD) output is an open-drain output
which requires a pull-up resistor. When the output voltage
is 12% below its nominal voltage (660mV), PGD is pulled
low. It is held low until the output voltage returns above
approximately -11% of nominal. PGD is held low during
start-up and will not be allowed to transition high until
soft-start is completed (when FB reaches 0.75V). There
Figure 4.
The resistor sensing circuit is shown in Figure 5 with R ILIM
= R1 and R SENSE = R4.
Resistive sensing operates similar to MOSFET sensing,
except that a resistor is used to improve accuracy. The
resistor connects between the MOSFET source and GND,
and the RILIM connects from the ILIM pin to the sense
resistor, as in Figure 5.
is a 1.5 μ s delay built into the PGD circuit to prevent false
transitions.
PGD also transitions low if the FB pin exceeds +20% of
nominal, which is also the over-voltage shutdown point. If
EN is low with VCC supplied, PGD is also pulled low.
Output Over-Voltage Protection
In steady state operation, when FB exceeds 20% of nomi-
nal, DL latches high and the low-side MOSFET is turned on.
DL stays high and the SMPS stays off until the EN input
+5V
VBAT
is toggled or VCC is recycled. There is a 1.5 μ s delay built
into the OVP detector to prevent false transitions. PGD is
also low after an OVP.
D1
Q1
+
C1
Output Under-Voltage Protection
BST
DH
LX
ILIM
VDD
DL
GND
C2
Q2
D2
L1
+
C3
Vout
When FB falls 30% below its trip point for eight consecutive
clock cycles, the output is shut off; the DL/DH drives are
pulled low to tri-state the MOSFETS, and the SMPS stays
off until the EN input is toggled or VCC is recycled.
SC412A
R1
R4
POR and UVLO
Under-voltage lockout circuitry (UVLO) inhibits switching
and tri-states the DH/DL drivers until VCC rises above 4.4V.
An internal power-on reset (POR) occurs when VCC exceeds
4.4V, which resets the fault latch and soft-start counter, to
prepare the PWM for switching. At this time the SC412A
Figure 5.
will come out of UVLO and begin the soft-start cycle.
? 2006 Semtech Corp.
10
www.semtech.com
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