参数资料
| 型号： | SC412AMLTRT |
| 厂商： | Semtech |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-MLP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 325kHz |
| 占空比： | 90% |
| 电源电压： | 3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-MLP |
| 包装： | 标准包装 |
| 其它名称： | SC412AMLDKR |
NOT RECOMMENDED FOR NEW DESIGN
POWER MANAGEMENT
Layout Guidelines (continued)
SC412A
1) There should be a very small input loop between
the input capacitors, MOSFETs, inductor, and output
capacitors. Locate the input decoupling capacitors
directly at the MOSFETs.
2) The phase node should be a large copper pour, but still
compact since this is the noisiest node.
3) The power GND connection between the input capacitors,
low-side MOSFET, and output capacitors should be as
small as is practical, with wide traces or planes.
2) Route DL, DH and LX (low side FET gate drive, high side
FET gate drive and phase node) to the chip using wide
traces, with multiple vias if using more than one layer.
These connections are to be as short as possible for
loop minimization, with a length to width ratio less than
20:1 to minimize impedance. DL is the most critical
gate drive, with power GND as its return path. LX is the
noisiest node in the circuit, switching between VBAT and
ground at high frequencies, thus should be kept as short
as practical. DH has LX as its return path. DL, DH, LX,
and BST are high-noise signals and should be kept well
away from sensitive signals, particularly FB and VOUT.
4) The impedance of the power GND connection between
the low-side MOSFET and the GND pin should be
minimized. This connection must carry the DL drive
current, which has high peaks at both rising and
falling edges. Use multiple layers and multiple vias to
minimize impedance, and keep the distance as short
as practical.
Finally, connecting the control and switcher power sections
should be accomplished as follows:
1) Route the VOUT feedback trace in a “quiet” layer, away
from noise sources.
3) BST is also a noisy node and should be kept as short as
possible. The high-side DH driver is relies on the boost
capacitor to provide the DH drive current, so the boost
capacitor must be placed near the IC and connect to the
BST and LX pins using short, wide traces to minimize
impedance.
4) Connect the GND pin on the chip to the VCC decoupling
capacitor and then drop vias directly to the ground
plane.
Locate the current limit resistor RLIM at the chip with a
kelvin connection to the drain of the lower MOSFET at the
phase node, and minimize the copper area of the ILIM
trace.
? 2006 Semtech Corp.
17
www.semtech.com
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