参数资料
型号: SC4508AMLTRT
厂商: Semtech
文件页数: 17/21页
文件大小: 0K
描述: IC REG CTRLR BST INV PWM 12-MLPQ
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 97%
电源电压: 2.7 V ~ 15 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 12-VQFN 裸露焊盘
包装: 标准包装
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC4508AMLDKR
SC4508A
POWER MANAGEMENT
Application Information (Cont.)
R 2 =
1
s p 1 C 2
≈ 2 . 03 k ?
bandwidth is reduced in order to reject some high
frequency noises. In the final working circuit, the loop
transfer function should be measured using network
C 3 =
≈ 2 . 92 nF
use R 2 = 2k ? .
Since S zRHP <s z1 , it is further calculated that::
1
R 2 ? s zRHP
use C 3 = 3.3nF. The Bode plot of the loop transfer
function (magnitude and phase) is shown in Figure 10.
analyzer and compared with the design to ensure circuit
stability under different line and load conditions. The load
transient response behavior is further tested and
measured to meet the specification.
Layout Guidelines
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, attention
60
60
43.33
must be paid to the PCB layouts. The goal of layout
optimization is to place components properly and identify
the high di/dt loops to minimize them. The following
20 ? log ( T ( f )
0
)
26.67
10
6.67
guideline should be used to ensure proper functions of
the converters.
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
100 1 . 10 1 . 10 1 . 10 1 . 10
10 ? 10
? 40
23.33
40
1
1
10
3 4 5 6
f 5
2. Start the PCB layout by placing the power components
first. Arrange the power circuit to achieve a clean
power flow route. Put all the connections on one side
of the PCB with wide copper filled areas if possible.
3. The VDD bypass capacitors should be placed next to
the VDD and PGND, AGND pins respectively.
4. Separate the power ground from the signal ground.
In SC4508A, the power ground PGND connection
? 80
80
100
should make PFET driving current loop as small as
possible. The signal ground AGND should be tied to
the negative terminal of the output capacitor.
5. The trace connecting the feedback resistors to the
180
π
arg ( T ( f ) )
120
140
160
output should be short, direct and far away from the
noise sources such as switching node and switching
components. Minimize the traces between OUT and
the gates of the PFETs to reduce their impedance to
drive the MOSFET.
7. Minimize the loop including input capacitors, top/
100 1 . 10 1 . 10
1 . 10 1 . 10
10 × 10
? 180 180
1
1
10
f
3 4
5 6
5
bottom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
8. Maximize the trace width of the loop connecting the
Figure 10. The loop transfer function Bode plot of the
buck-boost example.
It is clear that the resulted crossover frequency is about
1 kHz with phase margin 90 o .
In some initial prototypes, if the circuit noise makes the
control loop jitter, it is suggested to use a bigger C 3 value
than the calculated one here. Effectively, the converter
inductor, PFET and the output capacitors.
9. Connect the ground of the feedback divider and the
compensation components directly to the AGND pin
of the SC4508A by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible.
? 2007 Semtech Corp.
17
www.semtech.com
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