参数资料
| 型号： | SC4518HSETRT |
| 厂商： | Semtech |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK 2A 8-SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出数： | 1 |
| 输入电压： | 4.4 V ~ 24 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 600kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SO 裸露焊盘 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC4518HSEDKR |
SC4518H
POWER MANAGEMENT
Application Information (Cont.)
Where:
Layout Guidelines:
ω p 1 =
1
R L ? C
In order to achieve optimal electrical and thermal
performance for high frequency converters, special
attention must be paid to the PCB layouts. The goal of
One integrator is added at origin to increase the DC gain.
ω Z is used to cancel the power stage pole ω P1 so that the
loop gain has –20dB/dec rate when it reaches 0dB line.
ω P2 is placed at half switching frequency to reject high
frequency switching noises. Figure 4 gives the asymptotic
diagrams of the power stage with current loop closed
and its loop gain.
Mag
Loop gain T(s)
layout optimization is to identify the high di/dt loops and
minimize them. The following guidelines should be used
to ensure proper operation of the converters.
1. A ground plane is suggested to minimize switching
noises and trace losses and maximize heat
transferring.
2. Start the PCB layout by placing the power components
first. Arrange the power circuit to achieve a clean
power flow route. Put all power connections on one
side of the PCB with wide copper filled areas if
ω p1
ω Z
Power stage
ω C ω P2
ω
possible.
3. The V IN bypass capacitor should be placed next to
the V IN and GND pins.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from any
noise sources such as switching node and switching
components.
5. Minimize the loop including input capacitor, the
for given switching corner frequency ω C = 2 π f .
2. Place an integrator at the origin to increase DC and
Figure 4. Asymptotic diagrams of power stage with
current loop closed and its loop gain.
The design guidelines for the SC4518H applications are
as following:
1. Set the loop gain crossover corner frequency ω C
c
low frequency gains.
3. Select ω Z such that it is placed at ω P1 to obtain a
-20dB/dec rate to go across the 0dB line.
4. Place a high frequency compensator pole
ω P2 ( ω P2 = π f s ) to get the maximum attenuation of
the switching ripple and high frequency noise with
the adequate phase lag at ω C.
SC4518H and freewheeling diode D 2 . This loop
passes high di/dt current. Make sure the trace width
is wide enough to reduce copper losses in this loop.
6. Maximize the trace width of the loop connecting the
inductor, freewheeling diode D 2 and the output
capacitor.
7. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4518H by using a separate ground trace.
8. Connect Pin 4 to a large copper area to remove the
IC heat and increase the power capability of the
SC4518H. A few feedthrough holes are required to
connect this large copper area to a ground plane to
further improve the thermal environment of the
SC4518H. The traces attached to other pins should
be as wide as possible for the same purpose.
? 2007 Semtech Corp.
11
www.semtech.com
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